WM8983GEFLSLASHV datasheet(91/124 Pages) WOLFSON

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Production Data

WM8983

PD, Rev 4.3, May 2010

GENERAL PURPOSE INPUT/OUTPUT

The WM8983 has three dual purpose input/output pins.

•

CSB/GPIO1: CSB / GPIO1 pin

•

L2/GPIO2: Left channel line input / headphone detection input

•

R2/GPIO3: Right channel line input / headphone detection input

The GPIO2 and GPIO3 functions are provided for use as jack detection inputs.

The GPIO1 and GPIO2 functions are provided for use as jack detection inputs or general purpose

outputs.

The default configuration for the CSB/GPIO1 is to be an input.

When setup as an input, the CSB/GPIO1 pin can either be used as CSB or for jack detection,

depending on how the MODE pin is set.

Table 63 illustrates the functionality of the GPIO1 pin when used as a general purpose output.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

GPIO

Control

2:0

GPIO1SEL

000

CSB/GPIO1 pin function select:

000= input (CSB/jack detection:

depending on MODE setting)

001 = reserved

010 = Temp ok

011 = Amute active

100 = PLL clk output

101 = PLL lock

110 = logic 0

111 = logic 1

GPIO1POL

GPIO1 Polarity invert

0 = Non inverted

1 = Inverted

5:4

OPCLKDIV

PLL Output clock division ratio

00 = divide by 1

01 = divide by 2

10 = divide by 3

11 = divide by 4

Table 63 CSB/GPIO Control

Note: If MODE is set to 3 wire mode, CSB/GPIO1 is used as CSB input irrespective of the

GPIO1SEL[2:0] bits.

For further details of the jack detect operation see the OUTPUT SWITCHING section.

OUTPUT SWITCHING (JACK DETECT)

When the device is operated using a 2-wire interface the CSB/GPIO1 pin can be used as a switch

control input to automatically disable one set of outputs and enable another; the most common use

for this functionality is as jack detect circuitry. The L2/GPIO2 and R2/GPIO3 pins can also be used

for this purpose.

The GPIO pins have an internal de-bounce circuit when in this mode in order to prevent the output

enables from toggling multiple times due to input glitches. This de-bounce circuit is clocked from a

slow clock with period 2

21 x MCLK and is enabled by the SLOWCLKEN bit.

Notes:

The SLOWCLKEN bit must be enabled for the jack detect circuitry to operate.

The GPIOPOL bit is not relevant for jack detection, it is the signal detected at the pin which is

used.

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