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WM8976CGEFL/V датащи(PDF) 15 Page - Wolfson Microelectronics plc

номер детали WM8976CGEFL/V
подробное описание детали  Stereo CODEC with Speaker Driver
PDF  114 Pages
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производитель  WOLFSON [Wolfson Microelectronics plc]
домашняя страница  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8976CGEFL/V датащи(HTML) 15 Page - Wolfson Microelectronics plc

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Production Data
WM8976
w
PD, Rev 4.5, November 2011
15
Test Conditions
DCVDD=1.8V,
DBVDD=AVDD=SPKVDD=3.3V,
DGND=AGND=SPKGND=0V,
TA=+25
oC,
Master
Mode,
fs=48kHz,
MCLK=256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
LRC propagation delay from BCLK falling edge
tDL
10
ns
ADCDAT propagation delay from BCLK falling edge
tDDA
10
ns
DACDAT setup time to BCLK rising edge
tDST
10
ns
DACDAT hold time from BCLK rising edge
tDHT
10
ns
AUDIO INTERFACE TIMING – SLAVE MODE
Figure 4 Digital Audio Data Timing – Slave Mode
Test Conditions
DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA=+25
oC, Slave Mode, fs=48kHz,
MCLK= 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
50
ns
BCLK pulse width high
tBCH
20
ns
BCLK pulse width low
tBCL
20
ns
LRC set-up time to BCLK rising edge
tLRSU
10
ns
LRC hold time from BCLK rising edge
tLRH
10
ns
DACDAT hold time from BCLK rising edge
tDH
10
ns
DACDAT setup time to BCLK rising edge
tDs
10
ns
ADCDAT propagation delay from BCLK falling edge
tDD
10
ns
Note:
BCLK period should always be greater than or equal to MCLK period.



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