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WM8976CGEFL/V датащи(PDF) 73 Page - Wolfson Microelectronics plc

номер детали WM8976CGEFL/V
подробное описание детали  Stereo CODEC with Speaker Driver
PDF  114 Pages
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производитель  WOLFSON [Wolfson Microelectronics plc]
домашняя страница  http://www.wolfsonmicro.com
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WM8976CGEFL/V датащи(HTML) 73 Page - Wolfson Microelectronics plc

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Production Data
WM8976
w
PD, Rev 4.5, November 2011
73
The PLL performs best when f2 is around 90MHz. Its stability peaks at N=8. Some example settings
are shown in Table 59.
MCLK
(MHz)
(F1)
DESIRED
OUTPUT
(MHz)
F2
(MHz)
PRESCALE
DIVIDE
POSTSCALE
DIVIDE
R
N
(Hex)
K
(Hex)
12
11.29
90.3168
1
2
7.5264
7
86C226
12
12.288
98.304
1
2
8.192
8
3126E8
13
11.29
90.3168
1
2
6.947446
6
F28BD4
13
12.288
98.304
1
2
7.561846
7
8FD525
14.4
11.29
90.3168
1
2
6.272
6
45A1CA
14.4
12.288
98.304
1
2
6.826667
6
D3A06E
19.2
11.29
90.3168
2
2
9.408
9
6872AF
19.2
12.288
98.304
2
2
10.24
A
3D70A3
19.68
11.29
90.3168
2
2
9.178537
9
2DB492
19.68
12.288
98.304
2
2
9.990243
9
FD809F
19.8
11.29
90.3168
2
2
9.122909
9
1F76F7
19.8
12.288
98.304
2
2
9.929697
9
EE009E
24
11.29
90.3168
2
2
7.5264
7
86C226
24
12.288
98.304
2
2
8.192
8
3126E8
26
11.29
90.3168
2
2
6.947446
6
F28BD4
26
12.288
98.304
2
2
7.561846
7
8FD525
27
11.29
90.3168
2
2
6.690133
6
BOAC93
27
12.288
98.304
2
2
7.281778
7
482296
Table 59 PLL Frequency Examples
LOOPBACK
Setting the LOOPBACK register bit enables digital loopback. When this bit is set the output data from
the ADC audio interface is fed directly into the DAC data input.
COMPANDING
The WM8976 supports A-law and
-law and companding and linear mode on both transmit (ADC) and
receive (DAC) sides. Companding can be enabled on the DAC or ADC audio interfaces by writing the
appropriate value to the DAC_COMP or ADC_COMP register bits respectively.



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