HT47C06L datasheet(13/37 Pages) HOLTEK

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HT47C06L

Rev. 1.00

June 15, 2007

Bit No.

Label

Function

0~2

Unused bit, read as

²0²

3TE

Defines the TMR active edge of the timer/event counter:

In Event Counter Mode (TM1,TM0)=(0,1):

1:count on falling edge;

0:count on rising edge

In Pulse Width measurement mode (TM1,TM0)=(1,1):

1: start counting on the rising edge, stop on the falling edge;

0: start counting on the falling edge, stop on the rising edge

TON

To enable/disable timer counting

(0=disabled; 1=enabled)

TM0

TM1

To define the operating mode (TM1, TM0)

10=Timer mode (Internal clock: fSYS)

01=Event counter mode (External clock: A/D clock from pad RCIN)

11=Pulse width measurement mode (RCIN, fSYS)

00=Unused

Unused bit, read as

²0²

TMRC (22H) Register

the cycle measurement will function again as long as it

receives further transient pulse. Note that in this opera-

tion mode, the timer/event counter starts counting not

according to the logic level but according to the transient

edges. In the case of counter overflow, the counter is re-

loaded from the timer/event counter preload register

and issues interrupt request just like the other two

modes.

To enable the counting operation, the timer on bit (TON;

bit 4 of TMRC) should be set to 1. In the pulse width

measurement mode, the TON will automatically be

cleared after the measurement cycle is completed. But

in the other two modes, the TON can only be reset by in-

structions.

In the case of timer/event counter Off condition, writing

data to the timer/event counter preload register also re-

loads that data to the timer/event counter. But if the

timer/event counter turns On, data written to the

timer/event counter preload register is kept only in the

timer/event counter preload register. The timer/event

counter will still operate until overflow occurs.

When the timer/event counter (reading TMRAH) is read,

the clock will be blocked to avoid errors. As this may re-

sults in a counting error, this must be taken into consid-

eration.

It is strongly recommended to load first the desired

value into TMRBL, TMRBH, TMRAL, and TMRAH regis-

ters then turn on the related timer/event counter for

proper operation. Because the initial value of TMRBL,

TMRBH, TMRAL and TMRAH are unknown.

Example for Timer/event counter mode (disable interrupt):

clr tmrc

clr adcr.1

; set timer mode

clr intc.4

; clear timer/event counter interrupt request flag

mov a, low (65536-1000)

; give timer initial value

mov tmrbl, a

; count 1000 time and then overflow

mov a, high (65536-1000)

mov tmrbh, a

mov a, 01010000b

; timer clock source=fSYS and timer on

mov tmrc, a

p10:

clr wdt

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