HT47C06L datasheet(9/37 Pages) HOLTEK

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HT47C06L

Rev. 1.00

June 15, 2007

gram memory. Only the program counter is pushed onto

the stack. If the contents of the register and status regis-

ter (STATUS) is altered by the interrupt service program

which corrupts the desired control sequence, the con-

tents must be saved first.

The internal timer/event counter interrupt is initialized by

setting the timer/event counter interrupt request flag (TF;

bit 4 of INTC), caused by a timer A or timer B overflow.

When the interrupt is enabled, and the stack is not full

and the TF bit is set, a subroutine call to location 04H will

occur. The related interrupt request flag (TF) will be reset

and the EMI bit cleared to disable further interrupts.

The time base interrupt is initialized by setting the time

base interrupt request flag (TBF; bit 5 of INTC), caused

by a regular time base signal. When the interrupt is en-

abled, and the stack is not full and the TBF bit is set, a

subroutine call to location 08H will occur. The related in-

terrupt request flag (TBF) will be reset and the EMI bit

cleared to disable further interrupts.

During the execution of an interrupt subroutine, other in-

terrupt acknowledgments are held until the RETI in-

struction is executed or the EMI bit and the related

interrupt control bit are set to 1 (if the stack is not full). To

return from the interrupt subroutine, RET or RETI in-

struction may be invoked. RETI will set the EMI bit to en-

able an interrupt service, but RET does not.

Interrupts occurring in the interval between the rising

edges of two consecutive T2 pulses, will be serviced on

the latter of the two T2 pulses, if the corresponding inter-

rupts are enabled. In the case of simultaneous requests

the following table shows the priority that is applied.

These can be masked by resetting the EMI bit.

Interrupt Source

Priority

Vector

Timer/event counter interrupt

04H

Time base interrupt

08H

Oscillator Configuration

There is one external RC oscillator.

One method to generating the system clock is using an

external RC network. The HALT mode turned off the

system oscillator and ignores an external signal to con-

serve power.

If an RC oscillator is used, it requires that an external re-

sistor is connected between OSC1 and OSC2. The RC

oscillator provides the most cost effective solution. How-

ever, the oscillation frequency may vary with VDD, tem-

perature and process variations on the chip itself. It is

therefore not suitable for applications involving timing

sensitive operations or where accurate oscillator fre-

quencies are required.

Watchdog Timer

- WDT

The WDT clock source (fS)isfSYS. The timer is designed to

prevent software malfunctions or sequences from jump-

ing to unknown locations with unpredictable results. The

Watchdog timer can be disabled by mask option. If the

Watchdog timer is disabled, all the executions related to

the WDT result in no operation.

The

²HALT² instruction is executed, WDT still counts if fOSC

is on and can wake-up from HALT mode due to the WDT

time-out.

The WDT overflow under normal operation will initialize

²chip reset² and set the status bit TO. Whereas in the

HALT mode, the overflow will initialize a

²warm reset²

wherein only the program counter and stack pointer are

reset to zero. To clear the contents of the WDT, three

methods are adopted. The first is an external hardware

reset (a low level on the RES pin), the second is via soft-

ware instructions, and the third is via a

²HALT² instruc-

tion. The software instruction is CLR WDT. Any

execution of the CLR WDT instruction will clear the

WDT. The WDT may reset the chip due to time-out.

The WDT time-out period ranges from fS/2

15~f

S/2

16. The

²CLR WDT² instruction only clears the last two-stage of

the WDT.

Bit No.

Label

Function

EMI

Controls the master or global interrupt (1=enabled; 0=disabled)

ETI

Controls the timer/event counter interrupt (1=enabled; 0=disabled)

ETBI

Controls the time base interrupt (1=enabled; 0=disabled)

Unused bit, read as

²0²

Timer/event counter interrupt request flag (1=active; 0=inactive)

TBF

Time base interrupt request flag (1=active; 0=inactive)

6~7

Unused bit, read as

²0²

INTC (0BH) Register

R C O s c i l l a t o r

O S C 1

O S C 2

System Oscillator

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