SPEAR300 datasheet(15/83 Pages) STMICROELECTRONICS

15 / 83 page

SPEAr300

Architecture overview

Doc ID 16324 Rev 2

15/83

2.6

RTC oscillator

The RTC provides a 1-second resolution clock. This keeps time when the system is inactive

and can be used to wake the system up when a programmed alarm time is reached. It has a

clock trimming feature to compensate for the accuracy of the 32.768 kHz crystal and a

secured time update.

2.7

Multichannel DMA controller

Within its basic subsystem, SPEAr300 provides an DMA controller (DMAC) able to service

up to 8 independent DMA channels for sequential data transfers between single source and

destination (i.e., memory-to-memory, memory-to-peripheral, peripheral to- memory, and

peripheral-to-peripheral).

Each DMA channel can support a unidirectional transfer, with internal four-word FIFO per

channel.

2.8

Embedded memory units

●

32 Kbytes of BootROM

●

Up to 57 Kbytes of SRAM

The size of available SRAM varies according to the peripheral configuration mode See

Table 10.:

●

57 Kbytes in modes 1 and 2

●

8 Kbytes in modes 3 to 13.

2.9

Mobile DDR/DDR2 memory controller

SPEAr300 integrates a high performances multi-channel memory controller able to support

low power Mobile DDR and DDR2 double data rate memory devices. The multi-port

architecture ensures memory is shared efficiently among different high-bandwidth client

modules.

It has 6 internal ports. One of them is reserved for register access during the controller

initialization while the other five are used to access the external memory.

It also include the physical layer (PHY) and some DLLs that allow fine tuning of all the timing

parameters to maximize the data valid windows at any frequency in the allowed range.

2.10

Serial memory interface

SPEAr300 provides a serial memory interface (SMI) to SPI-compatible off-chip memories.

These serial memories can be used for both data storage and code execution.

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