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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SPEAR300 датащи(PDF) 62 Page - STMicroelectronics |
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SPEAR300 датащи(HTML) 62 Page - STMicroelectronics |
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62 / 83 page  Timing requirements SPEAr300 62/83 Doc ID 16324 Rev 2 6.3 I2C timing characteristics The characterization timing is done considering an output load of 10 pF on SCL and SDA. The operating conditions are V = 0.90 V, TA=125° C in worst case and V =1.10 V, TA= 40° C in best case. Figure 17. I2C output pins Figure 18. I2C input pins The flip-flops used to capture the incoming signals are re-synchronized with the AHB clock (HCLK): so, no input delay calculation is required. Those values are referred to the common internal source clock which has a period of: tHCLK = 6 ns. Table 31. Output delays for I2C signals Parameter Min Max Unit tHCLK->SCLH 8.1067 11.8184 ns tHCLK->SCLL 7.9874 12.6269 ns tHCLK->SDAH 7.5274 11.2453 ns tHCLK->SDAL 7.4081 12.0530 ns Set Q Q D Clr Set Q Q D Clr HCLK SCL SDA |
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