STW82102B datasheet(45/67 Pages) STMICROELECTRONICS

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STW82102B

I2C bus interface

Doc ID 018516 Rev 2

45/67

9.4

Device calibration through the I2C interface

9.4.1

VCO calibration procedure (I2C interface)

The calibration of the VCO center frequency is activated by setting the SERCAL bit of the

MUTE & CALIBRATION register to ’1’.

To program the device ensuring a correct VCO calibration, the following procedure is

required before every channel change:

Program all the Registers using a multi-byte write sequence with the desired setting:

–

Functional Mode

–

B and A counters

–

R counter

–

VCO amplitude

–

Charge Pump

–

Prescaler Modulus

–DAC

–

Mixer and LO Control

–

all bits of the MUTE & CALIBRATION Register (0x05) set to ’0’.

Program the MUTE & CALIBRATION register using a single-byte write sequence (sub-

address 0x05) with the SERCAL bit set to ’1’.

The maximum allowed PFD frequency (FPFD) to perform the calibration process is 1 MHz. If

the desired FPFD is higher than 1 MHz the following steps are needed:

Perform all the step of the above calibration procedure programming the desired VCO

frequency with a proper setting of R, B and A counter so that FPFD results lower than

1MHz.

Once calibration is completed, program all the Registers by using a multi-byte write

sequence (Functional Mode, B and A counters, R counter, VCO amplitude, Charge

Pump, Prescaler Modulus, DAC, Mixer and LO Control) with the proper settings for the

desired VCO and PFD frequencies.

9.4.2

Power ON sequence (I2C interface)

At power-on the device is configured in power-down mode.

In order to guarantee correct setting of the internal circuitry after the power on, the following

steps must be followed:

Power up the device

Provide the Reference clock

Implement the first programming sequence with a proper delay time between the STOP

condition of the multi-byte write sequence and that of the single-byte write sequence

(see Figure 20). The Tdelay value must respect the following condition:

Fref is the reference clock frequency.

delay

1023

ref

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