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STW82102B датащи(PDF) 34 Page - STMicroelectronics

номер детали STW82102B
подробное описание детали  RF down converter with embedded integer-N synthesizer
PDF  67 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STW82102B датащи(HTML) 34 Page - STMicroelectronics

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I2C bus interface
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Doc ID 018516 Rev 2
9.1.2
START and STOP conditions
Figure 15.
START and STOP condition waveform
START condition
A START condition is identified by a HIGH to LOW transition of the data bus SDA while the
clock signal SCL is stable in the HIGH state. A Start condition must precede any command
for data transfer.
STOP condition
A STOP condition is identified by a transition of the data bus SDA from LOW to HIGH while
the clock signal SCL is stable in the HIGH state.. A STOP condition terminates
communications between the STW82102B and the Bus Master.
9.1.3
Byte format and acknowledge
Every byte (8 bits long) transferred on the SDA line must contain bits. Each byte must be
followed by an acknowledge bit. The MSB is transferred first.
An acknowledge bit indicates a successful data transfer. The transmitter, either master or
slave, releases the SDA bus after sending 8 bits of data. During the 9th clock pulse the
receiver pulls the SDA low to acknowledge the receipt of 8 bits of data.
Figure 16.
Byte format and acknowledge waveform
SCL
SDA
START
STOP
SCL
SDA
START
MSB
1
2
3
7
8
9
STOP
Acknowledgement
from receiver



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