STW82102B datasheet(24/67 Pages) STMICROELECTRONICS

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General description

STW82102B

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Doc ID 018516 Rev 2

8.1.2

Reference divider

The 10-bit programmable reference counter allows the input reference frequency to be

divided to produce the input clock to the PFD. The division ratio is programmed through the

digital interface.

8.1.3

Prescaler

The dual-modulus prescaler P/P+1 takes the CML clock from the VCO buffer and divides it

down to a manageable frequency for the CMOS A and B counters. The modulus (P) is

programmable and can be set to 16 or 19. It is based on a synchronous 4/5 core which

division ratio depends on the state of the modulus input.

8.1.4

A and B counters

The A (5 bits) and B (12 bits) counters, in conjunction with the selected dual modulus (16/17

or 19/20) prescaler make it possible to generate output frequencies which are spaced only

by the reference frequency divided by the reference division ratio. Thus, the division ratio

and the VCO output frequency are given by the following formulae:

where:

FVCO: VCO output frequency.

P: modulus of dual modulus prescaler (16 or 19 selected through the digital interface).

B: division ratio of the main counter.

A: division ratio of the swallow counter.

Fref: input reference frequency.

R: division ratio of the reference counter.

N: division ratio of the PLL

The following points should be noted:

●

For the VCO divider to work correctly, B must be higher than A.

●

A can take any value from 0 to 31.

●

Two PLL division ratio (N) ranges are possible, depending on the value of P:

–

256 to 65551 (when P=16)

–

361 to 77836 (when P=19).

VCO

() F

ref

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