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STLC3075 датащи(PDF) 18 Page - STMicroelectronics

номер детали STLC3075
подробное описание детали  Integrated POTS interface for home access gateway and WLL
PDF  36 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STLC3075 датащи(HTML) 18 Page - STMicroelectronics

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Application information
STLC3075
18/36
1.
CVPOS should be defined depending on the power supply current capability and maximum allowable ripple
2.
For low ripple application use 2x47m F in parallel.
3.
Can be saved if proper PCB layout avoid noise coupling on RD pin (high impedance input).
4.
RF1 sets the self generated battery voltage in RING and ACTIVE(Il=0) mode as shown in Table 11.
VBATR should be defined considering the ring peak level required (Vringpeak=VBATR - 6 V typ.). This relation is valid
providing that the VPOS power supply current capability and the RSENSE programming allow to source all the current
requested by the particular ringer load configuration
5.
For high efficiency in HI-Z mode coil resistance @125kHz must be < 3
Ω.
Table 11.
VBAT values in RING and ACTIVE modes
267k
Ω
280k
Ω
294k
Ω
300k
Ω
VBAT (ACTIVE)
-46V
-48V
-49V
-50V
VBATR (RING)
-62V
-65V
-68V
-70V



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