STLC3075_09 datasheet(16/36 Pages) STMICROELECTRONICS

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Application information

STLC3075

16/36

Application information

5.1

Layout recommendation

A properly designed PCB layout is a basic issue to guarantee a correct behavior and good

noise performance.

Particular care must be taken on the ground connection. Using the configurations shown on

Figure 10 and Figure 11 permits to avoid possible problems.

The ground of the power supply (VPOS) has to be connected to the center of the star, named

as SYSTEM-GND. This point should show a resistance as low as possible, that means it

should be a ground plane.

In particular to avoid noise problems the layout should prevent any coupling between the

DC/DC converter components and analog pins that are referred to AGND (ex: RD, IREF,

RTH, RLIM, VF). As a first recommendation the components CV, L, T1, D1, CVPOS, RSENSE

should be kept as close as possible to each other and isolated from the other components.

Additional improvements can be obtained

–

by decoupling the center of the star from the analog ground of STLC3075 using

small chokes

–

by adding a capacitor in the range of 100 nF between VPOS and AGND in order to

filter the switch frequency on VPOS

5.2

External components list

In order to properly define the external components value the following system parameters

have to be defined:

●

the AC input impedance shown by the SLIC at the line terminals Zs to which the return

loss measurement is referred. It can be real (typ. 600

Ω) or complex.

●

the AC balance impedance, it is the equivalent impedance of the line ‘Zl’ used for

evaluation of the trans-hybrid loss performances (2/4 wire conversion). It is usually a

complex impedance.

●

the value of the two protection resistors Rp in series with the line termination.

●

the line impedance at the TTX frequency Zlttx

●

the metering pulse level amplitude measured at line termination VLOTTX. In case of low

order filtering, VLOTTX represents the amplitude (Vrms) of the fundamental frequency

component (typ. 12 or 16 kHz)

●

the pulse metering envelope rise and decay time constant

●

the slope of the ringing waveform

ΔV

TR/ΔT

●

the value of the constant current limit current ’Ilim’

●

the value of the off-hook current threshold ITH

●

the value of the ring trip rectified average threshold current IRTH

●

the value of the required self generated negative battery VBATR in ring mode (max value

is 70V). This value can be obtained from the desired ring peak level + 5V.

●

the value of the maximum current peak drawn from VPOS ’IPK’.

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