CDH2D09 datasheet(33/44 Pages) MAXIM

33 / 44 page

PMIC with Integrated Charger and

Smart Power Selector for Handheld Devices

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The MAX8671X uses external resistor-dividers to set the

step-down output voltages between 1V and VSYS. Use at

least 10µA of bias current in these dividers to ensure no

change in the stability of the closed-loop system. To set

the output voltage, select a value for the resistor con-

nected between FB_ and AGND (RFBL). The recom-

mended value is 100k

Ω. Next, calculate the value of the

resistor connected from FB_ to the output (RFBH):

REG1, REG2, and REG3 are optimized for high, medi-

um, and low output voltages, respectively. The highest

overall efficiency occurs with V1 set to the highest out-

put voltage and V3 set to the lowest output voltage.

PWM

The MAX8671X operates in either auto-PWM or forced-

PWM modes. At light load, auto PWM switches only as

needed to supply the load to improve light-load effi-

ciency of the step-down converter. At higher load cur-

rents (~100mA), the step-down converter transitions to

fixed 2MHz switching. Forced PWM always operates

with a constant 2MHz switching frequency regardless

of the load. This is useful in low-noise applications.

Permanently connect PWM high for forced-PWM appli-

cations or low for auto-PWM applications. Do not

change PWM on-the-fly.

Step-Down Dropout and Minimum Duty Cycle

All the step-down regulators are capable of operating

in 100% duty-cycle dropout; however, REG1 has been

optimized for this mode of operation. During 100%

duty-cycle operation, the high-side p-channel MOSFET

turns on constantly, connecting the input to the output

through the inductor. The dropout voltage (VDO) is cal-

culated as follows:

VDO = ILOAD (RP + RL)

where:

RP = p-channel power switch RDS(ON)

RL = external inductor ESR

The minimum duty cycle for all step-down regulators is

12.5% (typ), allowing a regulation voltage as low as 1V

over the full SYS operating range. REG3 is optimized

for low duty-cycle operation.

Step-Down Input Capacitors

The input capacitor in a step-down converter reduces

current peaks drawn from the power source and

reduces switching noise in the controller. The imped-

ance of the input capacitor at the switching frequency

must be less than that of the source impedance of the

supply so that high-frequency switching currents do not

pass through the input source.

The step-down regulator power inputs are critical dis-

continuous current paths that require careful bypass-

ing. In the PCB layout, place the step-down regulator

input bypass capacitors as close as possible to each

pair of switching regulator power input pins (PV_ to

PG_) to minimize parasitic inductance. If making con-

nections to these caps through vias, be sure to use

multiple vias to ensure that the layout does not insert

excess inductance or resistance between the bypass

cap and the power pins.

The input capacitor must meet the input ripple current

requirement imposed by the step-down converter.

Ceramic capacitors are preferred due to their low ESR

and resilience to power-up surge currents. Choose the

input capacitor so that its temperature rise due to input

ripple current does not exceed about +10°C. For a

step-down DC-DC converter, the maximum input ripple

current is half of the output current. This maximum input

ripple current occurs when the step-down converter

operates at 50% duty factor (VIN = 2 x VOUT).

Bypass each step-down regulator input with a 4.7µF

ceramic capacitor from PV_ to PG_. Use capacitors

that maintain their capacitance over temperature and

DC bias. Ceramic capacitors with an X7R or X5R tem-

perature characteristic generally perform well. The

capacitor voltage rating should be 6.3V or greater.

Step-Down Output Capacitors

The output capacitance keeps output ripple small and

ensures control loop stability. The output capacitor

must have low impedance at the switching frequency.

Ceramic, polymer, and tantalum capacitors are suit-

able, with ceramic exhibiting the lowest ESR and lowest

high-frequency impedance. The MAX8671X requires at

least 20µF of output capacitance, which is best

achieved with two 10µF ceramic capacitors in parallel.

As the case sizes of ceramic surface-mount capacitors

decrease, their capacitance vs. DC bias voltage char-

acteristic becomes poor. Due to this characteristic, it is

possible for 0805 capacitors to perform well while 0603

capacitors of the same value might not. The MAX8671X

requires a nominal output capacitance of 20µF; howev-

er, after their DC bias voltage derating, the output

capacitance must be at least 15µF.

FBH

FBL

OUT

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