CDH2D09 datasheet(20/44 Pages) MAXIM

20 / 44 page

PMIC with Integrated Charger and

Smart Power Selector for Handheld Devices

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Pin Description

NAME

FUNCTION

USUS

USB Suspend Digital Input. As shown in Table 1, driving USUS high suspends the DC or USB inputs

if they are configured as a USB power input.

2DC

DC Power Input. DC is capable of delivering 1A to SYS. DC supports both AC adaptors and USB

inputs. As shown in Table 1, the DC current limit is controlled by PEN1, PEN2, USUS, and RDISET.

USB

USB Power Input. USB is capable of delivering 0.5A to SYS. As shown in Table 1, the USB current

limit is controlled by PEN1, PEN2, and USUS.

FB5

Feedback Input for REG5. Connect FB5 to the center of a resistor voltage-divider from OUT5 to

AGND to set the REG5 output voltage from 0.6V to VPV5.

PV5

Power Input for REG5. Connect PV5 to SYS, or a supply between 1.7V and VSYS. Bypass PV5 to

power ground with a 1µF ceramic capacitor.

OUT5

Linear Regulator Power Output. OUT5 is internally pulled to AGND by 1k

Ω in shutdown.

PG2

Power Ground for the REG2 Step-Down Regulator

LX2

Inductor Switching Node for REG2. LX2 is internally pulled to PG2 by 1k

Ω in shutdown.

PV2

Power Input for the REG2 Step-Down Regulator. Connect PV2 to SYS. Bypass PV2 to PG2 with a

4.7µF ceramic capacitor.

CEN

Active-Low Charger Enable Input. Pull CEN low to enable the charger, or drive CEN high to disable

charging. The battery charger is also disabled when USUS is high.

FB2

Feedback Input for REG2. Connect FB2 to the center of a resistor voltage-divider from the REG2

output capacitors to AGND to set the output voltage from 1V to VSYS.

DOK

Active-Low, Open-Drain DC Power-OK Output. DOK is low when VDC is within its valid operating

range.

FB4

Feedback Input for REG4. Connect FB4 to the center of a resistor voltage-divider from the REG4

output capacitors to AGND to set the output voltage from 0.6V to VPV4.

Reference Noise Bypass. Bypass BP with a low-leakage 0.01µF ceramic capacitor for reduced noise

on the LDO outputs.

OUT4

Linear Regulator Power Output. OUT4 is internally pulled to AGND in shutdown.

PV4

Power Input for REG4. Connect PV4 to SYS, or a supply between 1.7V and VSYS. Bypass PV4 to

power ground with a 1µF ceramic capacitor.

BVSET

Battery Regulation Voltage Set Node. Drive BVSET low to set the regulation voltage to 4.1V. Connect

BVSET to VL or leave unconnected to set the regulation voltage to 4.2V. Connect BVSET to AGND

through a 50k

Ω resistor to set the regulation voltage to 4.350V.

AGND

Ground. AGND is the low-noise ground connection for the internal circuitry.

FB1

Feedback Input for REG1. Connect FB1 to the center of a resistor voltage-divider from the REG1

output capacitors to AGND to set the output voltage from 1V to VSYS.

Regulator Enable Input. Drive EN high to enable all regulator outputs. The sequencing is shown in

Figure 11. Drive EN low to disable the regulators.

PWM

Forced-PWM Input. Connect PWM high for forced-PWM operation on REG1, REG2, and REG3.

Connect PWM low for auto PWM operation. Do not change PWM on-the-fly. See the PWM section

for more information.

PV1

Power Input for the REG1 Step-Down Regulator. Connect PV1 to SYS. Bypass PV1 to PG1 with a

4.7µF ceramic capacitor.

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