LPC4088 datasheet(89/123 Pages) NXP

89 / 123 page

LPC408X_7X

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Objective data sheet

Rev. 1 — 17 September 2012

89 of 123

NXP Semiconductors

LPC408x/7x

32-bit ARM Cortex-M4 microcontroller

[1]

Tcy(clk) = (SSPCLKDIV  (1 + SCR)  CPSDVSR) / fmain. 1The clock cycle time derived from the SPI bit rate

Tcy(clk) is a function of the main clock frequency fmain, the SSP peripheral clock divider (SSPCLKDIV), the

SSP SCR parameter (specified in the SSP0CR0 register), and the SSP CPSDVSR parameter (specified in

the SSP clock prescale register).

[2]

Tamb = 40 C to 85 C; VDD(3V3) = 3.0 V to 3.6 V.

[3]

Tcy(clk) = 12  Tcy(PCLK).

[4]

Tamb = 25 C; VDD(3V3) = 3.3 V.

SSP slave

Tcy(PCLK)

PCLK cycle time

Tcy(clk)

clock cycle time

[3]

120

tDS

data set-up time

in SPI mode

[3][4]

14.8

tDH

data hold time

in SPI mode

[3][4]

tv(Q)

data output valid time in SPI mode

[3][4]

-6.3

th(Q)

data output hold time in SPI mode

[3][4]

2.4

Fig 22. SSP master timing in SPI mode

Table 22.

Dynamic characteristics: SSP pins in SPI mode

CL =10 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design.

Symbol

Parameter

Conditions

Min

Max

Unit

SCK (CPOL = 0)

MOSI

MISO

Tcy(clk)

tclk(H)

tclk(L)

tDS

tDH

tv(Q)

DATA VALID

th(Q)

SCK (CPOL = 1)

DATA VALID

MOSI

MISO

tDS

tDH

DATA VALID

th(Q)

DATA VALID

tv(Q)

CPHA = 1

CPHA = 0

002aae829

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