LPC4088 datasheet(2/123 Pages) NXP

2 / 123 page

LPC408X_7X

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Objective data sheet

Rev. 1 — 17 September 2012

2 of 123

NXP Semiconductors

LPC408x/7x

32-bit ARM Cortex-M4 microcontroller

 JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four watch

points.

 System tick timer.

 System:

 Multilayer AHB matrix interconnect provides a separate bus for each AHB master.

AHB masters include the CPU, and General Purpose DMA controller. This

interconnect provides communication with no arbitration delays unless two masters

attempt to access the same slave at the same time.

 Split APB bus allows for higher throughput with fewer stalls between the CPU and

DMA. A single level of write buffering allows the CPU to continue without waiting for

completion of APB writes if the APB was not already busy.

 Embedded Trace Macrocell (ETM) module supports real-time trace.

 Boundary scan for simplified board testing.

 Memory:

 512 kB on-chip flash program memory with In-System Programming (ISP) and

In-Application Programming (IAP) capabilities. The combination of an enhanced

flash memory accelerator and location of the flash memory on the CPU local

code/data bus provides high code performance from flash.

 Up to 96 kB on-chip SRAM includes:

64 kB of main SRAM on the CPU with local code/data bus for high-performance

CPU access.

Two 16 kB peripheral SRAM blocks with separate access paths for higher

throughput. These SRAM blocks may be used for DMA memory as well as for

general purpose instruction and data storage.

 Up to 4032 byte on-chip EEPROM.

 LCD controller, supporting both Super-Twisted Nematic (STN) and Thin-Film

Transistors (TFT) displays.

 Dedicated DMA controller.

 Selectable display resolution (up to 1024

 768 pixels).

 Supports up to 24-bit true-color mode.

 External Memory Controller (EMC) provides support for asynchronous static memory

devices such as RAM, ROM and flash, as well as dynamic memories such as single

data rate SDRAM.

 Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer

matrix that can be used with the SSP, I2S, UART, CRC engine, Analog-to-Digital and

Digital-to-Analog converter peripherals, timer match signals, GPIO, and for

memory-to-memory transfers.

 Serial interfaces:

 Quad SPI Flash Interface (SPIFI) with four lanes and up to 40 MB per second.

 Ethernet MAC with MII/RMII interface and associated DMA controller. These

functions reside on an independent AHB.

 USB 2.0 full-speed dual port device/host/OTG controller with on-chip PHY and

associated DMA controller.

 Five UARTs with fractional baud rate generation, internal FIFO, DMA support, and

RS-485/EIA-485 support. One UART (UART1) has full modem control I/O, and one

UART (USART4) supports IrDA, synchronous mode, and a smart card mode

conforming to ISO7816-3.

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