LPC4088 datasheet(39/123 Pages) NXP

39 / 123 page

LPC408X_7X

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Objective data sheet

Rev. 1 — 17 September 2012

39 of 123

NXP Semiconductors

LPC408x/7x

32-bit ARM Cortex-M4 microcontroller

[11] Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 1 MHz specification. It requires an external pull-up to provide output

functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. Open-drain

configuration applies to all functions on this pin.

[12] 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis.

[13] This pad can be powered from VBAT.

[14] Pad provides special analog functionality.

[15] If the RTC is not used, these pins can be left floating.

[16] When the main oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding

is preferred to reduce susceptibility to noise). XTAL2 should be left floating.

Functional description

7.1 Architectural overview

The ARM Cortex-M4 includes three AHB-Lite buses: the system bus, the I-code bus, and

the D-code bus. The I-code and D-code core buses are faster than the system bus and

are used similarly to Tightly Coupled Memory (TCM) interfaces: one bus dedicated for

instruction fetch (I-code) and one bus for data access (D-code). The use of two core

buses allows for simultaneous operations if concurrent operations target different devices.

The LPC408x/7x use a multi-layer AHB matrix to connect the ARM Cortex-M4 buses and

other bus masters to peripherals in a flexible manner that optimizes performance by

allowing peripherals that are on different slaves ports of the matrix to be accessed

simultaneously by different bus masters.

7.2 ARM Cortex-M4 processor

The ARM Cortex-M4 processor is running at frequencies of up to 120 MHz. The processor

executes the Thumb-2 instruction set for optimal performance and code size, including

hardware division, single-cycle multiply, and bit-field manipulation. A Memory Protection

Unit (MPU) supporting eight regions is included.

7.3 ARM Cortex-M4 Floating Point Unit (FPU)

Remark: The FPU is available on parts LP4088/78/76.

The FPU supports single-precision floating-point computation functionality in compliance

with the ANSI/IEEE Standard 754-2008. The FPU provides add, subtract, multiply, divide,

multiply and accumulate, and square root operations. It also performs a variety of

conversions between fixed-point, floating-point, and integer data formats.

7.4 On-chip flash program memory

The LPC408x/7x contain up to 512 kB of on-chip flash program memory. A new two-port

flash accelerator maximizes performance for use with the two fast AHB-Lite buses.

7.5 EEPROM

The LPC408x/7x contains up to 4032 byte of on-chip byte-erasable and

byte-programmable EEPROM data memory.

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