TM16ER72HP 16777216 BY 72BIT

TM16ER72LP 16777216 BY 72BIT

EXTENDEDDATAOUT BUFFERED DYNAMIC RAM MODULES

SMMS694 − AUGUST 1997

7

POST OFFICE BOX 1443

electrical characteristics over recommended ranges of supply voltage and ambient temperature

(unless otherwise noted) (continued)

TM16ER72LP

PARAMETER

TEST CONDITIONS†

’16ER72LP-40

’16ER72LP-50

’16ER72LP-60

UNIT

PARAMETER

TEST CONDITIONS†

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

VOH

High-level output

IOH = − 2 mA

LVTTL

2.4

2.4

2.4

V

VOH

High-level output

voltage

IOH = − 100 µA

LVCMOS

VDD −0.2

VDD −0.2

VDD −0.2

V

VOL

Low-level output

IOL = 2 mA

LVTTL

0.4

0.4

0.4

V

VOL

Low-level output

voltage

IOL = 100 µA

LVCMOS

0.2

0.2

0.2

V

II

Input current

(leakage)

VDD = 3.6 V,

VI = 0 V to 3.9 V,

All others = 0 V to VCC

± 20

± 20

± 20

µA

IO

Output current

(leakage)

VDD = 3.6 V,

VO = 0 V to VDD,

CASx high

± 20

± 20

± 20

µA

ICC1‡§

Average read- or

write-cycle

current

VDD = 3.6 V,

Minimum cycle

2 250

1 800

1 620

mA

ICC2

Average standby

VIH = 2 V (LVTTL),

After one memory cycle,

RASx and CASx high

18

18

18

mA

ICC2

Average standby

current

VIH = VDD − 0.2 V (LVCMOS),

After one memory cycle,

RASx and CASx high

9

9

9

mA

ICC3‡§

Average refresh

current

(RAS-only

refresh or CBR)

VDD = 3.6 V,

Minimum cycle,

RASx cycling,

CASx high (RASx-only refresh),

RASx low after CASx low (CBR)

2 250

1 800

2 250

mA

ICC4‡¶

Average EDO

current

VDD = 3.6 V,

tHPC = MIN,

RASx low,

CASx cycling

2 520

1 980

1 620

mA

ICC5

Average CBR

refresh current

VDD = 3.6 V,

Minimum cycle,

RASx low after CASx low

2 880

2 340

1 980

mA

† For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements.

‡ Measured with outputs open

§ Measured with a maximum of one address change while RASx = VIL

¶ Measured with a maximum of one address change during each EDO cycle, tHPC