TM16ER72HP 16777216 BY 72BIT

TM16ER72LP 16777216 BY 72BIT

EXTENDEDDATAOUT BUFFERED DYNAMIC RAM MODULES

SMMS694 − AUGUST 1997

4

POST OFFICE BOX 1443

buffered dual-in-line memory module and components

The buffered dual-in-line memory module and components include:

functional block diagram for the TM16ER72xP

CAS

OE

W

RAS

U0

RAS0

WE0

OE0

CAS0

DQ[0:3]

CAS

OE

W

RAS

UB0

DQ[32:35]

DQ[0:3]

DQ[0:3]

CAS

OE

W

RAS

U1

DQ[4:7]

CAS

OE

W

RAS

UB1

DQ[36:39]

DQ[0:3]

DQ[0:3]

CAS

OE

W

RAS

U2

DQ[8:11]

CAS

OE

W

RAS

UB2

DQ[40:43]

DQ[0:3]

DQ[0:3]

CAS

OE

W

RAS

U3

DQ[12:15]

CAS

OE

W

RAS

UB3

DQ[44:47]

DQ[0:3]

DQ[0:3]

CAS

OE

W

RAS

U4

DQ[16:19]

CAS

OE

W

RAS

UB4

DQ[48:51]

DQ[0:3]

DQ[0:3]

CAS

OE

W

RAS

U5

DQ[20:23]

CAS

OE

W

RAS

UB5

DQ[52:55]

DQ[0:3]

DQ[0:3]

CAS

OE

W

RAS

U6

DQ[24:27]

CAS

OE

W

RAS

UB6

DQ[56:59]

DQ[0:3]

DQ[0:3]

CAS

OE

W

RAS

U7

DQ[28:31]

CAS

OE

W

RAS

UB7

DQ[60:63]

DQ[0:3]

DQ[0:3]

CAS

OE

W

RAS

U8

CB[0:3]

CAS

OE

W

RAS

UB8

CB[4:7]

DQ[0:3]

DQ[0:3]

A0

U[0:8]

B0

UB[0:8]

A[1:n]

A[1:n]: U[0:8], UB[0:8]

VDD

VSS

U[0:8], UB[0:8]

U[0:8], UB[0:8]

Two 0.1

µF (Minimum)

per DRAM

RAS2

WE2

OE2

CAS4