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Application Conditions Not Shown in Block Diagram

V

OUT2

V

IN1

V

IN2

EN

SEQ

V

OUT1

V

SENSE1

Pg1

MR2

RESET

MR1

V

SENSE2

V

OUT2

V

I

V

OUT1

MR1

RESET

10 F

m

MR2

EN

>2V

<0.7V

250kW

0.1 F

m

10 F

m

TPS70751PWP

(Fixed-OutputOption)

0.1 F

m

Explanation of Timing Diagram

TPS70751-EP

DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATOR

WITH POWER-UP SEQUENCING FOR SPLIT-VOLTAGE DSP SYSTEMS

SLVS718 – DECEMBER 2006

APPLICATION INFORMATION (continued)

tied to MR2, and MR1 is left unconnected and is, therefore, at logic high.

EN is initially high; therefore, both regulators are off and PG1 and RESET are at logic low. With SEQ at logic

(tied to PG1) are at logic high, RESET is pulled to logic high after a 120-ms delay. When EN is returned to logic

high, both devices turn off and both PG1 (tied to MR2) and RESET return to logic low.

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