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1.8V

V

IN1

V

IN2

EN

SEQ

V

OUT1

V

SENSE1

PG1

MR2

RESET

MR1

V

SENSE2

V

OUT2

TPS70751PWP

5V

3.3V

I/O

MR1

Core

0.1

F

m

RESET

10

F

m

10

F

m

0.1

F

m

DSP

MR2

PG1

EN

250kW

>2V

<0.7V

250kW

>2V

<0.7V

>2V

<0.7V

TPS70751-EP

DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATOR

WITH POWER-UP SEQUENCING FOR SPLIT-VOLTAGE DSP SYSTEMS

SLVS718 – DECEMBER 2006

The device is enabled when the enable (EN) pin is connected to a low-level input voltage. The output voltages of

the two regulators are sensed at the V

The input signal at the sequence (SEQ) pin controls the power-up sequence of the two regulators. When the

device is enabled and SEQ is pulled high or left open, V

reaches approximately 83% of its regulated output voltage. At that time, V

below 83% (i.e., overload condition), V

is turned on first. SEQ is connected to an internal pullup current source.

For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator

is turned off (disabled).

The power good (PG1) pin reports the voltage conditions at V

SVS for the circuitry supplied by regulator 1.

The TPS70751 features a RESET (SVS, POR, or power-on reset). The RESET output initiates a reset in DSP

systems and related digital applications in the event of an undervoltage condition. RESET indicates the status of

V

and MR2 are in the logic high state, RESET goes to a high-impedance state after a 120-ms delay. RESET goes

to logic low state when V

regulated voltage. To monitor V

The device has an undervoltage lockout (UVLO) circuit that prevents the internal regulators from turning on until

V

AVAILABLE OPTIONS

REGULATOR 1

REGULATOR 2

TSSOP

(PWP)

–55

°C to 125°C

3.3 V

1.8 V

TPS70751MPWPREP

2

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