SST49LF004A datasheet(17/36 Pages) SST

17 / 36 page

Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

S71161-06-000

9/01

504

TABLE

8: PIN DESCRIPTION

Symbol

Pin Name

Type1

Interface

Functions

FWH

A10-A0

Address

Inputs for low-order addresses during Read and Write operations.

Addresses are internally latched during a Write cycle. For the pro-

gramming interface, these addresses are latched by R/C# and share

the same pins as the high-order address inputs.

DQ7-DQ0

Data

I/O

To output data during Read cycles and receive input data during

Write cycles. Data is internally latched during a Write cycle. The out-

puts are in tri-state when OE# is high.

OE#

Output Enable

To gate the data output buffers

WE#

Write Enable

To control the Write operations

Interface

Configuration Pin

This pin determines which interface is operational. When held high,

programmer mode is enabled and when held low, FWH mode is

enabled. This pin must be setup at power-up or before return from

reset and not change during device operation. This pin is internally

pulled- down with a resistor between 20-100 K

Ω.

INIT#

Initialize

This is the second reset pin for in-system use. This pin is internally

combined with the RST# pin; If this pin or RST# pin is driven low,

identical operation is exhibited.

ID[3:0]

Identification Inputs

These four pins are part of the mechanism that allows multiple parts

to be attached to the same bus. The strapping of these pins is used

to identify the component.The boot device must have ID[3:0]=0000

and it is recommended that all subsequent devices should use

sequential up-count strapping. These pins are internally pulled-down

with a resistor between 20-100 K

Ω.

FGPI[4:0]

General Purpose Inputs

These individual inputs can be used for additional board flexibility.

The state of these pins can be read through GPI_REG register.

These inputs should be at their desired state before the start of the

PCI clock cycle during which the read is attempted, and should

remain in place until the end of the Read cycle. Unused GPI pins

must not be floated.

TBL#

Top Block Lock

When low, prevents programming to the Boot Block sectors at top of

memory. When TBL# is high it disables hardware write protection for

the top block sectors. This pin cannot be left unconnected.

FWH[3:0]

FWH I/Os

I/O

I/O Communications

CLK

Clock

To provide a clock input to the control unit

FWH4

FWH Input

Input Communications

RST#

Reset

To reset the operation of the device

WP#

Write Protect

When low, prevents programming to all but the highest addressable

blocks. When WP# is high it disables hardware write protection for

these blocks. This pin cannot be left unconnected.

R/C#

Row/Column Select

Select For the Programming interface, this pin determines whether

the address pins are pointing to the row addresses, or to the column

addresses.

RES

Reserved

These pins must be left unconnected.

VDD

Power Supply

To provide power supply (3.0-3.6V)

VSS

Ground

Circuit ground (OV reference) Every VSS pin must be grounded.

No Connection

Unconnected pins

T8.3 504

1. I = Input, O = Output

SST49LF004A датащи(PDF) 17 Page - Silicon Storage Technology, Inc

SST49LF004A датащи(HTML) 17 Page - Silicon Storage Technology, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

датащи скачать

ссылки URL