SST49LF004A datasheet(21/36 Pages) SST

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Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

S71161-06-000

9/01

504

AC CHARACTERISTICS (FWH MODE)

TABLE 16: READ/WRITE CYCLE TIMING PARAMETERS (FWH MODE), VDD =3.0-3.6V

Symbol

Parameter

Min

Max

Units

TCYC

Clock Cycle Time

TSU

Data Set Up Time to Clock Rising

TDH

Clock Rising to Data Hold Time

TVAL1

1. Minimum and maximum times have different loads. See PCI spec.

Clock Rising to Data Valid

TBP

Byte Programming Time

µs

TSE

Sector-Erase Time

TBE

Block-Erase Time

TSCE

Chip-Erase Time

100

TON

Clock Rising to Active (Float to Active Delay)

TOFF

Clock Rising to Inactive (Active to Float Delay)

T16.3 504

TABLE 17: AC INPUT/OUTPUT SPECIFICATIONS (FWH MODE)

Symbol

Parameter

Min

Max

Units

Conditions

IOH(AC)

Switching Current High

-12 VDD

-17.1(VDD-VOUT)

Equation C1

1. See PCI spec.

0 < VOUT ≤ 0.3VDD

0.3VDD < VOUT < 0.9VDD

0.7VDD < VOUT <VDD

(Test Point)

-32 VDD

VOUT=0.7VDD

IOL(AC)

Switching Current Low

16 VDD

26.7 VOUT

Equation D1

VDD >VOUT ≥0.6VDD

0.6VDD > VOUT > 0.1VDD

0.18VDD > VOUT > 0

(Test Point)

38 VDD

VOUT=0.18VDD

ICL

Low Clamp Current

-25+(VIN+1)/0.015

-3 < VIN ≤ -1

ICH

High Clamp Current

25+(VIN-VDD-1)/0.015

VDD+4 > VIN ≤ VDD+1

slewr2

2. PCI specification output load is used.

Output Rise Slew Rate

V/ns

0.2VDD-0.6VDD load

slewf2

Output Fall Slew Rate

V/ns

0.6VDD-0.2VDD load

T17.3 504

TABLE 18: RESET TIMING PARAMETERS, VDD =3.0-3.6V (FWH MODE)

Symbol

Parameter

Min

Max

Units

TPRST

VDD stable to Reset Low

TKRST

Clock Stable to Reset Low

100

µs

TRSTP

RST# Pulse Width

100

TRSTF

RST# Low to Output Float

TRST1

1. There will be a latency of TRSTE if a reset procedure is performed during a Program or Erase operation.

RST# High to FWH4 Low

µs

TRSTE

RST# Low to reset during Sector-/Block-Erase or Program

µs

T18.5 504

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