SST49LF004A datasheet(2/36 Pages) SST

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Advance Information

2 Mbit / 3 Mbit / 4 Mbit / 8 Mbit Firmware Hub

SST49LF002A / SST49LF003A / SST49LF004A / SST49LF008A

S71161-06-000

9/01

504

any given voltage range, the SuperFlash technology uses

less current to program and has a shorter erase time, the

total energy consumed during any Erase or Program oper-

ation is less than alternative flash memory technologies.

The SST49LF00xA products provide a maximum Byte-

Program time of 20 µsec. The entire memory can be

erased and programmed byte-by-byte typically in 15 sec-

onds for an 8-Mbit device, when using status detection

features such as Toggle Bit or Data# Polling to indicate the

completion of Program operation. The SuperFlash tech-

nology provides fixed Erase and Program time, indepen-

dent of the number of Erase/Program cycles that have

performed. Therefore the system software or hardware

does not have to be calibrated or correlated to the cumu-

lated number of Erase/Program cycles as is necessary

with alternative flash memory technologies, whose Erase

and Program time increase with accumulated Erase/Pro-

gram cycles.

To protect against inadvertent write, the SST49LF00xA

devices employ hardware and software data (SDP) protec-

tion schemes. It is offered with typical endurance of

100,000 cycles. Data retention is rated at greater than 100

years.

To meet high density, surface mount requirements, the

SST49LF00xA device is offered in 32-lead TSOP and 32-

lead PLCC packages. See Figures 7 and 8 for pinouts and

Table 8 for pin descriptions.

Mode Selection and Description

The SST49LF00xA flash memory devices can operate in

two distinct interface modes: the Firmware Hub Interface

(FWH) mode and the Parallel Programming (PP) mode.

The IC (Interface Configuration pin) is used to set the

interface mode selection. If the IC pin is set to logic High,

the device is in PP mode; while if the IC pin is set Low,

the device is in the FWH mode. The IC selection pin must

be configured prior to device operation. The IC pin is

internally pulled down if the pin is not connected. In FWH

mode, the device is configured to interface with its host

using Intel’s Firmware Hub proprietary protocol. Commu-

nication between Host and the SST49LF00xA occurs via

the 4-bit I/O communication signals, FWH [3:0] and the

FWH4. In PP mode, the device is programmed via an 11-

bit address and an 8-bit data I/O parallel signals. The

address inputs are multiplexed in row and column

selected by control signal R/C# pin. The column

addresses are mapped to the higher internal addresses,

and the row addresses are mapped to the lower internal

addresses. See the Device Memory Maps in Figures 3

through 6 for address assignments.

FIRMWARE HUB (FWH) MODE

Device Operation

The FWH mode uses a 5-signal communication interface,

FWH[3:0] and FWH4, to control operations of the

SST49LF00xA. Operations such as Memory Read and

Memory Write uses Intel FWH propriety protocol. JEDEC

Standard SDP (Software Data Protection) Byte-Program,

Sector-Erase and Block-Erase command sequences are

incorporated into the FWH memory cycles. Chip-Erase is

only available in PP Mode.

The device enters standby mode when FWH4 is high and

no internal operation is in progress. The device is in ready

mode when FWH4 is low and no activity is on the FWH bus.

Firmware Hub Interface Cycles

Addresses and data are transferred to and from the

SST49LF00xA by a series of “fields,” where each field con-

tains 4 bits of data. ST49LF00xA supports only single-byte

read and writes, and all fields are one clock cycle in length.

Field sequences and contents are strictly defined for Read

and Write operations. Addresses in this section refer to

addresses as seen from the SST49LF00xA’s “point of

view,” some calculation will be required to translate these to

the actual locations in the memory map (and vice versa) if

multiple memory device is used on the bus. Tables 1 and 2

list the field sequences for Read and Write cycles.

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