SN8P1602AS datasheet(51/94 Pages) SONIX

51 / 94 page

SN8P1600

8-bit micro-controller

SONiX TECHNOLOGY CO., LTD

Page 51

Revision 1.94

8 TIMERS

WATCHDOG TIMER (WDT)

The watchdog timer (WDT) is a binary up counter designed for monitoring program execution. If the program goes into

the unknown status by noise interference, WDT overflow signal raises and resets MCU. The instruction that clear the

watchdog timer (“B0BSET

FWDRST“) should be executed within a certain period. If an instruction that clears the

watchdog timer is not executed within the period and the watchdog timer overflows, reset signal is generated and

system is restarted. The watchdog timer rate has two rates for high/low speed mode. WDT rate selection is handled by

oscillator code option. The watchdog timer disables at power down mode.

0CAH

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

OSCM

WDRST

CPUM0

CLKMD

STPHX

Read/Write

R/W

After reset

WDRST: Watchdog timer reset bit. 0 = Non reset, 1 = clear the watchdog timer counter.

Note: The bit 0, 4, 5, 7 must be “0”, or the system will be error.

Watchdog timer overflow table.

Code option of High_Clk

Watchdog timer overflow time

4M_X’tal / 12M_X’tal / RC

1 / ( fcpu

÷ 214 ÷ 16 ) = 293 ms, Fosc=3.58MHz

32K_X’tal

1 / ( fcpu

÷ 28 ÷ 16 ) = 500 ms, Fosc=32768Hz

Note: The watchdog timer can be enabled or disabled by the code option.

Example: An operation of watchdog timer is as following. To clear the watchdog timer counter in the top

of the main routine of the program.

Main:

B0BSET

FWDRST

; Clear the watchdog timer counter.

CALL

SUB1

CALL

SUB2

JMP

MAIN

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