AD9518-2 datasheet(48/64 Pages) AD

48 / 64 page

AD9518-2

Data Sheet

Rev. C | Page 48 of 64

Table 44. PLL

Reg.

Addr.

(Hex)

Bits

Name

Description

0x010

PFD polarity

Sets the PFD polarity. Negative polarity is for use (if needed) with external VCO/VCXO only. The on-chip VCO requires

positive polarity; Bit 7 = 0b.

0: positive; higher control voltage produces higher frequency (default).

1: negative; higher control voltage produces lower frequency.

[6:4]

CP current

Charge pump current (with CPRSET = 5.1 kΩ).

ICP (mA)

0.6.

1.2.

1.8.

2.4.

3.0.

3.6.

4.2.

4.8 (default).

[3:2]

CP mode

Charge pump operating mode.

Charge Pump Mode

High impedance state.

Force source current (pump up).

Force sink current (pump down).

Normal operation (default).

[1:0]

PLL power-down

PLL operating mode.

Mode

Normal operation.

Asynchronous power-down (default).

Normal operation.

Synchronous power-down.

0x011

[7:0]

14-bit R divider,

Bits[7:0] (LSB)

R divider LSBs—lower eight bits (default = 0x01).

0x012

[5:0]

14-bit R divider,

Bits[13:8] (MSB)

R divider MSBs—upper six bits (default = 0x00).

0x013

[5:0]

6-bit A counter

A counter (part of N divider) (default = 0x00).

0x014

[7:0]

13-bit B counter,

Bits[7:0] (LSB)

B counter (part of N divider)—lower eight bits (default = 0x03).

0x015

[4:0]

13-bit B counter,

Bits[12:8] (MSB)

B counter (part of N divider)—upper five bits (default = 0x00).

0x016

Set CP pin to VCP/2

Sets the CP pin to one-half of the VCP supply voltage.

0: CP normal operation (default).

1: CP pin set to VCP/2.

Reset R counter

Resets R counter (R divider).

0: normal (default).

1: holds the R counter in reset.

Reset A, B counters

Resets A and B counters (part of N divider).

0: normal (default).

1: holds the A and B counters in reset.

Reset all counters

Resets R, A, and B counters.

0: normal (default).

1: holds the R, A, and B counters in reset.

B counter bypass

B counter bypass. This is valid only when operating the prescaler in FD mode.

0: normal (default).

1: B counter is set to divide-by-1. This allows the prescaler setting to determine the divide for the N divider.

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