LTC4155 datasheet(43/52 Pages) LINER

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LTC4155

4155fc

The generalized form of the NTC equations provided in

the Operations section are included above to facilitate

interpretation of the thermistor analog to digital converter

results using the custom bias network. If only RBIAS was

modified, let αTEMP_RANGE = 0.

Choosing the Input Multiplexer/Overvoltage

Protection MOSFETs

The LTC4155 contains an internal charge pump voltage

doubler to drive N-channel MOSFETS via the USBGT and

WALLGT pins. The gate-source voltage available to drive

the input multiplexer/protection FETS is approximately

equal to the input voltage, typically 4V to 6V. To ensure

that the FET channels are sufficiently enhanced to provide

a low resistance conduction path, the FET threshold volt-

age should be less than approximately 2.5V. Total gate

leakage current should be below 1μA to guarantee ample

charge pump output voltage. The gate oxide breakdown

voltage should be higher than 7V. The FET RDS(ON) will

negatively impact the switching regulator and battery

charger efficiency at high current levels. With two protec-

tion FETs in series (MN1 and MN3, MN2 and MN4), the

total resistance is the sum of the individual RDS(ON)s. This

combined resistance should be negligible compared to the

typical 80mΩ to 90mΩ resistance of the LTC4155 internal

switches for maximum performance. The drain breakdown

voltage of devices MN1 and MN2 must be appropriate for

the level of overvoltage protection desired. The drains will

be exposed to the full magnitude of applied input voltage.

The drains of devices MN3 and MN4 are exposed only to

the operating voltage range of the LTC4155. Therefore

the drain breakdown voltage of devices MN3 and MN4

should be rated for at least 7V. Table 36 lists several suit-

able N-channel transistors. Transistors with lower BVDSS

may be appropriate for devices MN3 and MN4 if reverse

protection is not required. Note that resistors R1 and R2

must also be sized appropriately for power dissipation

based on the level of overvoltage protection desired, as

explained in the Operation section.

Table 36. Recommended N-Channel Input Multiplexer MOSFETs

MANUFACTURER

PART

NUMBER

RDS(ON)

(mΩ)

VT (V)

BVDSS (V)

Fairchild

FDMC8651

4.3

1.1

Fairchild

FDMC8030

10.7

2.8

Vishay

Si7938DP

5.6

2.5

APPLICATIONS INFORMATION

αT = κSPAN

•NTCVAL

+κOFFSET

−κSPAN •NTCVAL – κOFFSET

⎡

⎣

⎢

⎤

⎦

⎥αBIAS −αTEMP_RANGE

κSPAN •NTCVAL +κOFFSET

−κSPAN •NTCVAL – κOFFSET

⎡

⎣

⎢

⎤

⎦

⎥αBIAS −αTEMP_RANGE

⎛

⎝

⎜

⎞

⎠

⎟+ β

Figure 10. Dual-Input Overvoltage Protection

Alternate Input Power Configurations

For applications requiring only a single input, the external

circuit required for overvoltage protection is considerably

simplified. Only a single N-channel MOSFET and resistor

are required for positive voltage protection, as shown in

Figure 11, and OVGCAP may be left unconnected. Applica-

tions using the USB On-The-Go step-up regulator should

connect R1 to USBSNS and the gate of MN1 to USBGT.

Applications not using USB On-The-Go may use either the

USBSNS/USBGT pins or the WALLSNS/WALLGT pins. The

unused pins may be left unconnected.

For dual-input applications requiring reverse-voltage

protection, no additional power transistors are required.

The circuit in Figure 12 provides positive protection up to

VBUS

TO USB

INPUT

TO WALL

INPUT

OVGCAP

USBGT

USBSNS

WALLGT

LTC4155

WALLSNS

4155 F10

MN1

MN3

MN2

MN4

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