LTC4155 datasheet(23/52 Pages) LINER

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LTC4155

4155fc

2.5mA Linear Suspend Mode

The LTC4155 can supply a small amount of current from

VBUS to VOUT to power the system and reduce battery

discharge when the product has access to a suspended

USB port. When the system load current is less than the

current available from the suspended USB port, the volt-

age at VOUT will be regulated to 4.35V. If the system load

current exceeds USB input current limit, the voltage at

VOUT will fall to the battery voltage and any supplemental

current above that available from the USB port will be

supplied by the battery. CLPROG2 will servo to 103mV

in current limit. Battery charging is disabled in suspend

mode. Either the USB or WALL input may utilize this current

limited suspend mode by programming the appropriate

setting in the respective USBILIM or WALLILIM register.

Ideal Diode and Minimum VOUT Controller

The LTC4155 features an ideal diode controller to ensure

that the system is provided with sufficient power even

when input power is absent or insufficient. This requires

an external PMOS transistor with its source connected

to CHGSNS, gate to BATGATE, and drain to BATSNS. The

controller modulates the gate voltage of the PMOS tran-

sistor to allow current to flow from the battery to VOUT to

power the system while blocking current in the opposite

direction to prevent overcharging of the battery.

The ideal diode controller has several modes of operation.

When input power is available and the battery is charging,

the PMOS gate will generally be grounded to maximize

conduction between the switching regulator and the battery

for maximum efficiency. If the battery is deeply discharged,

the LTC4155 will automatically increase the impedance

between the switching regulator and the battery enough

to prevent VOUT from falling below approximately 3.5V.

Power to the system load is always prioritized over battery

charge current. Increasing the impedance between VOUT

and the battery does not necessarily affect the battery

charge current, but it may do so for one of the following

two reasons:

1. The charge current will be limited to prevent excessive

power dissipation in the external PMOS as it becomes

more resistive. Charge current reduction begins when

the voltage across the PMOS reaches approximately

250mV, and can reduce the charge current as low as

8% full scale. Maximum power dissipation in the PMOS

is limited to approximately 1W with RPROG = 499Ω.

2. When limited power is available to the switching regula-

tor because either the programmed input current limit

or input undervoltage current limit is active, charge

current will automatically be reduced to prioritize

power delivery to the system at VOUT. VOUT will be

maintained at 3.5V as long as possible without exceed-

ing the input power limitation. If the system load alone

requires more power than is available from the input

after charge current has been reduced to zero, VOUT

must fall to the battery voltage as the battery begins

providing supplemental power.

When input power is available, but the battery charger is

disabled or charging has terminated, VOUT and the bat-

tery are normally disconnected to prevent overcharging

the battery. If the power required by the system should

exceed the power available from the input, either because

of input current limit or input undervoltage current limit,

VOUT will fall to the battery voltage and any additional cur-

rent required by the load will be supplied by the battery

through the ideal diode.

When input power is unavailable, the ideal diode switches

to a low power mode which maximizes conduction and

power transmission efficiency between VOUT and the bat-

tery by grounding the PMOS gate.

Finally, when ship-and-store mode is activated, the ideal

diode is shut down and BATGATE is driven to the battery

voltage to prevent conduction through the PMOS. Note

that with a single FET, conduction to VOUT is still possible

through the body connection diode. Refer to Low Power

Ship-and-Store Mode in the Operation section for more

information about this mode.

OPERATION

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