LTC3589 datasheet(44/50 Pages) LINER

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LTC3589/LTC3589-1/

LTC3589-2

3589fe

APPLICATIONS INFORMATION

The LTC3589 is optimized to support several families of

advanced portable applications processors including the

Marvell PXA3xx and PXA168 Xscale processors, the Fre-

escale i.MX family including the new i.MX53 and i.MX51,

the TI OMAP processors utilizing their Smart reflex, and

many additional ARM processors.

PXA3XX Monahans Processor Support

The PXA3XX processors are hard-coded to communicate

with a PMIC at specific command register addresses in

order to power up the processor supply rails from the

low power state. The LTC3589 I2C device address and

command register addresses map to PXA3xx command

address is 0x68. The key command register addresses

for PXA3xx support are the Output Voltage Enable (OVEN)

to OVEN bit 0 (enable step-down switching regulator 1).

VCC_SRAM/S_EN is mapped to OVEN bit 2 (enable step-

down switching regulator 3). The voltage change control

trols the dynamic voltage select and go bits required to

command a voltage change and slew when coming out

of low voltage standby or sleep modes into run mode.

The dynamic target voltage (xxDTV[1,2]) registers map

to the mandatory command register addresses. The full

17 supports Monahans, hard-coded I2C commands for

start-of-day operation, voltage-change sequence, supply

enable, and return-to-D0 state sequence.

The LTC3589 does not specifically reference the Mona-

hans SYS_EN and PWR_EN enable pins but supports

these signals with individual enable input pins EN[1-4]

and EN_LDO[2,34] that should be hard-wired to SYS_EN

or PWR_EN as required for proper system-level power

sequencing.

The LTC3589 RSTO signal is used to drive the Monahans

hard reset signal nRESET and is based on the state of

the always-active regulator output LDO1_STBY and by a

pushbutton hard reset request. The release of the RSTO

output is delayed a minimum of 10ms as required or as

long as 1s when the LTC3589 is reset using its pushbut-

ton controller.

PXA16X Armada Processor Support

LTC3589 includes spare register bits that can be accessed

by the processor for setting and recalling hibernate and

resume operation.

The keep-alive function allow a step-down switching

regulator to maintain system memory during a hibernate

shutdown state of the Armada processor.

i.MX53 and i.MX51 Processor Support

The LTC3589 has hardware features specifically designed

for the latest i.MX family of processors from Freescale

Semiconductor. The i.MX53 and i.MX51 control the

VSTB input pin of the LTC3589 to command transitions

between the run mode core voltage and the lower level

standby voltage. The run and standby voltage levels are

initially programmed in I2C command registers xxBTV1

and xxBTV2. When the VSTB pin is asserted high all four

dynamically controlled output supply rails will slew to the

xxBTV2 set point. When xxBTV1 and xxBTV2 are set at

the same value, as they are by default, then no slewing

occurs. This allows the single VSTB pin to control any

combination of the four DAC controlled regulators to slew

between two programmed output voltages. When VSTB is

de-asserted back to a zero value the regulators slew back

up to the xxBTV1 set point.

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