ADP1879ACPZ-0.3-R7 datasheet(28/40 Pages) AD

28 / 40 page

ADP1878/ADP1879

Data Sheet

Rev. A | Page 28 of 40

power dissipation across the internal LDO. Equation 3 shows the

power dissipation calculations for the integrated drivers and for

the internal LDO. Table 9 lists the thermal impedance for the

ADP1878/ADP1879, which are available in a 14-lead LFCSP_WD.

Table 9. Thermal Impedance for 14-Lead LFCSP_WD

Package

Thermal Impedance

14-Lead LFCSP_WD θJA

4-Layer Board

30°C/W

Figure 85 specifies the maximum allowable ambient temperature

that can surround the ADP1878/ADP1879 IC for a specified

high input voltage (VIN). Figure 85 illustrates the temperature

derating conditions for each available switching frequency for

low, typical, and high output setpoints for the 14-lead LFCSP_WD

package. All temperature derating criteria are based on a

maximum IC junction temperature of 125°C.

Figure 85. Ambient Temperature vs. VIN,

4-Layer Evaluation Board, CIN = 4.3 nF (High-/Low-Side MOSFET)

The maximum junction temperature allowed for the ADP1878/

ADP1879 IC is 125°C. This means that the sum of the ambient

temperature (TA) and the rise in package temperature (TR), which is

caused by the thermal impedance of the package and the internal

power dissipation, should not exceed 125°C, as dictated by the

following expression:

TJ = TR × TA

(1)

where:

TJ is the maximum junction temperature.

TR is the rise in package temperature due to the power

dissipated from within.

TA is the ambient temperature.

The rise in package temperature is directly proportional to its

thermal impedance characteristics. The following equation

represents this proportionality relationship:

TR = θJA × PDR(LOSS)

(2)

where:

θJA is the thermal resistance of the package from the junction to

the outside surface of the die, where it meets the surrounding air.

PDR(LOSS) is the overall power dissipated by the IC.

The bulk of the power dissipated is due to the gate capacitance of

the external MOSFETs and current running through the on-board

LDO. The power loss equations for the MOSFET drivers and

internal low dropout regulator (see the MOSFET Driver Loss

section and the Efficiency Consideration section) are:

PDR(LOSS) = [VDR × (fSWCupperFETVDR + IBIAS)] +

[VREG × (fSWClowerFET VREG + IBIAS)]

(3)

where:

CupperFET is the input gate capacitance of the high-side MOSFET.

ClowerFET is the input gate capacitance of the low-side MOSFET.

IBIAS is the dc current (2 mA) flowing into the high- and low-

side drivers.

VDR is the driver bias voltage (the low input voltage (VREG) minus

the rectifier drop (see Figure 83)).

VREG is the LDO output/bias voltage.

PDISS(LDO) = PDR(LOSS) + (VIN – VREG) × (fSW × CTOTAL ×

VREG + IBIAS

(4)

where PDISS(LDO) is the power dissipated through the pass device

in the LDO block across VIN and VREG.

PDR(LOSS) is the MOSFET driver loss.

VIN is the high voltage input.

VREG is the LDO output voltage and bias voltage.

CTOTAL is the CGD + CGS of the external MOSFET.

IBIAS is the dc input bias current.

For example, if the external MOSFET characteristics are θJA

(14-lead LFCSP_WD) = 30°C/W, fSW = 300 kHz, IBIAS = 2 mA,

CupperFET = 3.3 nF, ClowerFET = 3.3 nF, VDR = 4.62 V, and VREG = 5.0 V,

then the power loss is

PDR(LOSS) = [VDR × (fSWCupperFETVDR + IBIAS)] +

[VREG × (fSWClowerFETVREG + IBIAS)]

= (4.62 × (300 × 103 × 3.3 × 10−9 × 4.62 + 0.002)) +

(5.0 × (300 × 103 × 3.3 × 10−9 × 5.0 + 0.002))

= 57.12 mW

PDISS(LDO) = (VIN – VREG) × (fSW × CTOTAL × VREG + IBIAS) =

(13 V – 5 V) × (300 × 103 × 3.3 × 10−9 × 5 + 0.002)

= 55.6 mW

PDISS(TOTAL) = PDISS(LDO) + PDR(LOSS)

= 77.13 mW + 55.6 mW

= 132.73 mW

130

100

110

120

5.5

19.0

17.5

16.0

14.5

13.0

11.5

10.0

8.5

7.0

VIN (V)

300kHz

600kHz

1MHz

VOUT = 0.8V

VOUT = 1.8V

VOUT = HIGH SETPOINT

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