ADF4196BCPZ datasheet(3/28 Pages) AD

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Data Sheet

ADF4196

Rev. B | Page 3 of 28

SPECIFICATIONS

AVDD = DVDD1, DVDD2, DVDD3 = SDVDD = 3 V ± 10%; VP1, VP2 = 5 V ± 10%; VP3 = 5.35 V ± 5%; AGND1, AGND2 = DGND1, DGND2, DGND3 = 0 V;

RSET = 2.4 kΩ; dBm referred to 50 Ω; TA = TMIN to TMAX, unless otherwise noted. Operating temperature range = −40°C to +85°C.

Table 1.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

RF CHARACTERISTICS

RF Input Frequency (RFIN±)

0.4

GHz

See Figure 21 for input circuit

RF Input Sensitivity

−10

dBm

Maximum Allowable Prescaler Output

Frequency1

750

MHz

REFIN CHARACTERISTICS

REFIN Input Frequency

300

MHz

For f > 120 MHz, set REF/2 bit = 1 (Register R1)

REFIN Edge Slew Rate

300

V/µs

REFIN Input Sensitivity

0.7

VDD

V p-p

AC-coupled

0 to VDD

CMOS compatible

REFIN Input Capacitance

REFIN Input Current

±100

µA

PHASE DETECTOR

Phase Detector Frequency

MHz

CHARGE PUMP

ICP Up/Down

High Value

6.6

RSET = 2.4 kΩ

Low Value

104

µA

RSET = 2.4 kΩ

Absolute Accuracy

RSET Range

kΩ

Nominally RSET = 2.4 kΩ

ICP Three-State Leakage

ICP Up vs. Down Matching

0.1

0.75 V ≤ VCP ≤ VP1, VP2, VP3 − 1.5 V

ICP vs. VCP

0.75 V ≤ VCP ≤ VP1, VP2, VP3 − 1.5 V

ICP vs. Temperature

0.75 V ≤ VCP ≤ VP1, VP2, VP3 − 1.5 V

DIFFERENTIAL AMPLIFIER

Input Current

Output Voltage Range

1.4

VP3 − 0.3

VCO Tuning Range

1.8

VP3 − 0.8

Output Noise

nV/√Hz

At 20 kHz offset

LOGIC INPUTS

Input High Voltage, VIH

1.4

Input Low Voltage, VIL

0.7

Input Current, IINH, IINL

±1

µA

Input Capacitance, CIN

LOGIC OUTPUTS

Output High Voltage, VOH

VDD − 0.4

IOH = 500 µA

Output Low Voltage, VOL

0.4

IOL = 500 µA

POWER SUPPLIES

AVDD

2.7

3.3

DVDD1, DVDD2, DVDD3

AVDD

VP1, VP2

4.5

5.5

AVDD ≤ VP1, VP2 ≤ 5.5 V

VP3

5.0

5.65

VP1, VP2 ≤ VP3 ≤ 5.65 V

IDD (AVDD + DVDD1, DVDD2, DVDD3 +

SDVDD)

IDD (VP1 + VP2)

IDD (VP3)

IDD Power-Down

µA

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