ADF4196BCPZ datasheet(21/28 Pages) AD

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Data Sheet

ADF4196

Rev. B | Page 21 of 28

MUX REGISTER (R6) LATCH MAP AND TRUTH TABLE

DB15

M13

DB14

M12

DB13

M11

DB12

M10

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

C3 (1)

DB1

C2 (1)

DB0

C1 (0)

RESERVED

MUXOUT

CONTROL

BITS

SIGMA-DELTA

AND

LOCK DETECT MODES

M10

M11

ALL OTHER STATES

M12

M13

INIT STATE, DITHER OFF,

3ns LOCK DETECT THRESHOLD

DITHER ON

10ns LOCK DETECT THRESHOLD

RESERVED

SIGMA-DELTA MODES

3-STATE

DIGITAL LOCK DETECT

N DIVIDER OUTPUT

LOGIC HIGH

R DIVIDER OUTPUT

RESERVED

SERIAL DATA OUTPUT

LOGIC LOW

R DIVIDER/2 OUTPUT

N DIVIDER/2 OUTPUT

RESERVED

ICP TIMEOUT SIGNAL

SW1/SW2 TIMEOUT SIGNAL

SW3 TIMEOUT SIGNAL

RESERVED

MUXOUT

Figure 35. Bit Map and MUXOUT Truth Table for Register R6

R6, the mux register, is used to program MUXOUT, as well as

Σ-Δ and lock detect modes.

Control Bits

Σ-Δ and Lock Detect Modes

Bit DB15 to Bit DB12 are used to reconfigure certain PLL

operating modes. In the initialization sequence after power is

applied to the chip, the four bits must first be programmed to

all zeros. This initializes the PLL to a known state with dither

off in the Σ-Δ modulator and a 3 ns PFD error threshold in the

lock detect circuit.

To turn on dither in the Σ-Δ modulator, an additional write should

be made to Register R6 to program Bits[DB15:DB12] = 0011.

However, for lowest noise operation, it is best to leave dither off.

To change the lock detect threshold from 3 ns to 10 ns, perform

a separate write to R6 to program Bits[DB15:DB12] = 1001.

This separate write is needed for reliable lock detect operation

when the RF frequency is <2 GHz.

A write to R6 that programs Bits[DB15:DB12] = 0000 returns

operation to the default state with both dither off and a 3 ns

lock detect threshold.

Reserved Bits

For normal operation, the reserved bits (Bits[DB11:DB7]) must

be set to 00001.

MUXOUT Modes

These bits control the on-chip multiplexer, Pin 16 (see Figure 35

for the truth table). This pin is useful for diagnosis because it

allows the user to look at various internal points of the chip,

such as the R divider and the INT divider outputs.

In addition, it is possible to monitor the programmed timeout

counter intervals on MUXOUT. For example, if the ICP timeout

counter is programmed to 65 (with a 26 MHz PFD), then

following the next write to R0, a pulse width of 10 µs is

observed on the MUXOUT pin.

Digital lock detect is available via the MUXOUT pin.

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