SC508 datasheet(24/32 Pages) SEMTECH

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SC508/SC508A

Applications Information (continued)

cause a peak voltage on the capacitor according to the

following equation.

OUT

PEAK

RIPPLEMAX

OUT

MIN

COUT

Assuming a peak voltage V

PEAK of 1.98 (180mV rise upon

load release), and a 8A load release, the required capaci-

tance is shown by the next equation.

MIN

1.80

1.98

4.3

1.8

COUT

MIN = 272µF

If the load release is relatively slow, the output capacitance

can be reduced. At heavy loads during normal switching,

when the FB pin is above the 600mV reference, the DL

output is high and the low-side MOSFET is on. During this

time, the voltage across the inductor is approximately

-V

OUT. This causes a down-slope or falling di/dt in the

inductor. If the load di/dt is not faster than the -di/dt in

the inductor, then the inductor current will tend to track

the falling load current. This will reduce the excess induc-

tive energy that must be absorbed by the output capaci-

tor, therefore a smaller capacitance can be used.

The following can be used to calculate the needed capaci-

tance for a given dI

LOAD/dt. Peak inductor current is shown

by the next equation.

LPK = IMAX + 1/2 x IRIPPLEMAX

LPK = 8 + 1/2 x 4.3 = 10.2A

Current

Load

change

Rate

LOAD

MAX = maximum load release = 10A

OUT

LOAD

MAX

OUT

LPK

OUT

Example

LOAD

This would cause the output current to move from 10A to

zero in 4µs as shown by the following equation.

1.8

1.98

2.5

1.8

10.2

1.8

10.2

OUT

OUT = 198µF

Note that C

OUT is much smaller in this example, 198µF

compared to 272µF based on a worst-case load release. To

meet the two design criteria of minimum 272µF and

maximum 16.7mΩ ESR, select a capacitor rated at 330µF

and 6mΩ ESR.

It is recommended that an additional small capacitor with

a value of 1 to 10µF be placed in parallel with C

OUT in order

to filter high frequency switching noise.

Stability Considerations

Unstable operation is possible with adaptive on-time con-

trollers, and usually takes the form of double-pulsing or

ESR loop instability.

Double-pulsing occurs due to switching noise seen at the

FB input or because the FB ripple voltage is too low. This

causes the FB comparator to trigger prematurely after the

250ns minimum off-time has expired. In extreme cases

the noise can cause three or more successive on-times.

Double-pulsing will result in higher ripple voltage at the

output, but in most applications it will not affect opera-

tion. This form of instability can usually be avoided by

providing the FB pin with a smooth, clean ripple signal

that is at least 10mVp-p, which may dictate the need to

increase the ESR of the output capacitors. It is also impera-

tive to provide a proper PCB layout as discussed in the

Layout Guidelines section.

Another way to eliminate doubling-pulsing is to add a

small capacitor across the upper feedback resistor, as

shown in Figure 16. This capacitor should be left unpopu-

lated unless it can be confirmed that double-pulsing

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