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AFS090 датащи(PDF) 167 Page - Microsemi Corporation

номер детали AFS090
подробное описание детали  Fusion Family of Mixed Signal FPGAs
PDF  334 Pages
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производитель  MICROSEMI [Microsemi Corporation]
домашняя страница  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

AFS090 датащи(HTML) 167 Page - Microsemi Corporation

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Fusion Family of Mixed Signal FPGAs
R e visio n 2
2 - 151
Selectable Skew between Output Buffer Enable/Disable Time
The configurable skew block is used to delay the output buffer assertion (enable) without affecting
deassertion (disable) time.
Figure 2-105 • Block Diagram of Output Enable Path
Figure 2-106 • Timing Diagram (option1: bypasses skew circuit)
Figure 2-107 • Timing Diagram (option 2: enables skew circuit)
ENABLE (OUT)
Skew Circuit
Output Enable
(from FPGA core)
I/O Output
Buffers
ENABLE (IN)
MUX
Skew Select
ENABLE (IN)
ENABLE (OUT)
Less than
0.1 ns
Less than
0.1 ns
ENABLE (IN)
ENABLE (OUT)
1.2 ns
(typical)
Less than
0.1 ns



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