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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AFS090 датащи(PDF) 43 Page - Microsemi Corporation |
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AFS090 датащи(HTML) 43 Page - Microsemi Corporation |
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43 / 334 page  Fusion Family of Mixed Signal FPGAs R e visio n 2 2 - 27 Global Input Selections Each global buffer, as well as the PLL reference clock, can be driven from one of the following (Figure 2- 22): • 3 dedicated single-ended I/Os using a hardwired connection • 2 dedicated differential I/Os using a hardwired connection • The FPGA core Notes: 1. Represents the global input pins. Globals have direct access to the clock conditioning block and are not routed via the FPGA fabric. Refer to the "User I/O Naming Convention" section on page 2-160 for more information. 2. Instantiate the routed clock source input as follows: a) Connect the output of a logic element to the clock input of the PLL, CLKDLY, or CLKINT macro. b) Do not place a clock source I/O (INBUF or INBUF_LVPECL/LVDS) in a relevant global pin location. 3. LVDS-based clock sources are available in the east and west banks on all Fusion devices. Figure 2-22 • Clock Input Sources Including CLKBUF, CLKBUF_LVDS/LVPECL, and CLKINT + + Source for CCC (CLKA or CLKB or CLKC) Each shaded box represents an input buffer called out by the appropriate name: INBUF or INBUF_LVDS/LVPECL. To Core Routed Clock (from FPGA core) 2 Sample Pin Names GAA0 1 GAA1 1 GAA2 1 GAA[0:2]: GA represents global in the northwest corner of the device. A[0:2]: designates specific A clock source. |
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