AFS090 datasheet(58/334 Pages) MICROSEMI

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Device Architecture

2- 42

R e visio n 2

Flash Memory Block Pin Names

Table 2-19 • Flash Memory Block Pin Names

Interface Name

Width Direction

Description

ADDR[17:0]

Byte offset into the FB. Byte-based address.

AUXBLOCK

When asserted, the page addressed is used to access the auxiliary

block within that page.

BUSY

Out

When asserted, indicates that the FB is performing an operation.

CLK

User interface clock. All operations and status are synchronous to the

rising edge of this clock.

DATAWIDTH[1:0]

Data width

00 = 1 byte in RD/WD[7:0]

01 = 2 bytes in RD/WD[15:0]

1x = 4 bytes in RD/WD[31:0]

DISCARDPAGE

When asserted, the contents of the Page Buffer are discarded so that

a new page write can be started.

ERASEPAGE

When asserted, the address page is to be programmed with all zeros.

ERASEPAGE must transition synchronously with the rising edge of

CLK.

LOCKREQUEST

When asserted, indicates to the JTAG controller that the FPGA

interface is accessing the FB.

OVERWRITEPAGE

When asserted, the page addressed is overwritten with the contents of

the Page Buffer if the page is writable.

OVERWRITEPROTECT

When asserted, all program operations will set the overwrite protect bit

of the page being programmed.

PAGESTATUS

When asserted with REN, initiates a read page status operation.

PAGELOSSPROTECT

When asserted, a modified Page Buffer must be programmed or

discarded before accessing a new page.

PIPE

Adds a pipeline stage to the output for operation above 50 MHz.

PROGRAM

When asserted, writes the contents of the Page Buffer into the FB

page addressed.

RD[31:0]

Out

Read data; data will be valid from the first non-busy cycle (BUSY = 0)

after REN has been asserted.

READNEXT

When asserted with REN, initiates a read-next operation.

REN

When asserted, initiates a read operation.

RESET

When asserted, resets the state of the FB (active low).

SPAREPAGE

When asserted, the sector addressed is used to access the spare

page within that sector.

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