AFS090 datasheet(99/334 Pages) MICROSEMI

99 / 334 page

Fusion Family of Mixed Signal FPGAs

R e visio n 2

2 - 83

The third part of the Analog Quad is called the Gate Driver Block, and its output pin is named AG. This

section is used to drive an external FET. There are two modes available: a High Current Drive mode and

a Current Source Control mode. Both negative and positive voltage polarities are available, and in the

current source control mode, four different current levels are available.

The fourth section of the Analog Quad is called the Temperature Monitor Block, and its input pin name is

AT. This block is similar to the Voltage Monitor Block, except that it has an additional function: it can be

used to monitor the temperature of an external diode-connected transistor. It has a modified prescaler

and is limited to positive voltages only.

The Analog Quad can be configured during design time by Libero IDE; however, the ACM can be used to

change the parameters of any of these I/Os during runtime. This type of change is referred to as a

context switch. The Analog Quad is a modular structure that is replicated to generate the analog I/O

resources. Each Fusion device supports between 5 and 10 Analog Quads.

The analog pads are numbered to clearly identify both the type of pad (voltage, current, gate driver, or

temperature pad) and its corresponding Analog Quad (AV0, AC0, AG0, AT0, AV1, …, AC9, AG9, and

AT9). There are three types of input pads (AVx, ACx, and ATx) and one type of analog output pad (AGx).

Since there can be up to 10 Analog Quads on a device, there can be a maximum of 30 analog input pads

and 10 analog output pads.

Figure 2-63 • Analog Quad

Analog Quad

Voltage

Monitor Block

Current

Monitor Block

Prescaler

Digital

Input

Power

MOSFET

Gate Driver

Current

Monitor/Instr

Amplifier

Temperature

Monitor

Digital

Input

Digital

Input

Pads

To Analog MUX

To FPGA

(DAVOUTx)

To FPGA

(DACOUTx)

To FPGA

(DATOUTx)

On-Chip

Gate

Driver

Temperature

Monitor Block

Off-Chip

From FPGA

(GDONx)

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