AFS090 datasheet(108/334 Pages) MICROSEMI

108 / 334 page

Device Architecture

2- 92

R e visio n 2

Gate Driver

The Fusion Analog Quad includes a Gate Driver connected to the Quad's AG pin (Figure 2-72).

Designed to work with external p- or n-channel MOSFETs, the Gate driver is a configurable current sink

or source and requires an external pull-up or pull-down resistor. The AG supports 4 selectable gate drive

levels: 1 µA, 3 µA, 10 µA, and 30 µA (Figure 2-73 on page 2-93). The AG also supports a High Current

Drive mode in which it can sink 20 mA; in this mode the switching rate is approximately 1.3 MHz with

100 ns turn-on time and 600 ns turn-off time. Modeled on an open-drain-style output, it does not output a

voltage level without an appropriate pull-up or pull-down resistor. If 1 V is forced on the drain, the current

sinking/sourcing will exceed the ability of the transistor, and the device could be damaged.

The AG pad is turned on via the corresponding GDONx pin in the Analog Block macro, where x is the

number of the corresponding Analog Quad for the AG pad to be enabled (GDON0 to GDON9).

The gate-to-source voltage (Vgs) of the external MOSFET is limited to the programmable drive current

times the external pull-up or pull-down resistor value (EQ 5).

Vgs ≤ Ig × (Rpullup or Rpulldown)

EQ 5

The rate at which the gate voltage of the external MOSFET slews is determined by the current, Ig,

sourced or sunk by the AG pin and the gate-to-source capacitance, CGS, of the external MOSFET. As an

approximation, the slew rate is given by EQ 6.

dv/dt = Ig / CGS

EQ 6

Figure 2-72 • Gate Driver

Analog Quad

Voltage

Monitor Block

Current

Monitor Block

Power

Line Side

Load Side

Digital

Input

Power

MOSFET

Gate Driver

Current

Monitor / Instr

Amplifier

Temperature

Monitor

Digital

Input

Digital

Input

Pads

To Analog MUX

To FPGA

(DAVOUTx)

To FPGA

(DACOUTx)

To FPGA

(DATOUTx)

On-Chip

Gate

Driver

Temperature

Monitor Block

Off-Chip

Rpullup

From FPGA

(GDONx)

Prescaler

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