HT83XXX

Rev. 1.60

16

November 19, 2008

To guarantee that the system oscillator has started and

stabilized, the SST (System Start-up Timer) provides an

extra-delay of 1024 system clock pulses after a system

power up or when awakening from a HALT state.

When a system power up occurs, the SST delay is

added during the reset period. But when the reset co-

mes from the RES pin, the SST delay is disabled. Any

wake-up from HALT will enable the SST delay.

The functional unit chip reset status are shown below.

Program Counter

000H

Interrupt

Disable

Prescaler

Clear

WDT

Clear. After master reset,

WDT begins counting

Timer Counter

Off

Input/Output Ports

Input mode

Stack Pointer

Points to the top of the stack

Timer Counter 0/1

The TMR0/TMR1 is internal clock source only, i.e. (TM1, TM0) = (0, 1). There is a 3-bit prescaler (TMRS2, TMRS1,

TMRS0) which defines different division ratio of TMR0/TMR1

¢s clock source.

Bit No.

Label

Function

0~2

TMRS2,

TMRS1,

TMRS0

Defines the operating clock source (TMRS2, TMRS1, TMRS0)

000: clock source/2

001: clock source/4

010: clock source/8

011: clock source/16

100: clock source/32

101: clock source/64

110: clock source/128

111: clock source/256

3

TE

Defines the TMR0/TMR1 active edge of Timer Counter

4

TON

Enable/disable timer counting (0=disabled; 1=enabled)

5

¾

Unused bit, read as

²0²

6

7

TM0,

TM1

Defines the operating mode (TM1, TM0)

TMR0C (0EH)/TMR1C (11H) Register

Note:

TMR0C/TMR1C bit 3 always write

²0²

TMR0C/TMR1C bit 5 always write

²0²

TMR0C/TMR1C bit 6 always write

²1²

TMR0C/TMR1C bit 7 always write

²0²

S y s t e m C l o c k

8 - S t a g e

P r e s c a l e r

T i m e r C o u n t e r 0 / 1

P r e l o a d R e g i s t e r

D a t a B u s

R e l o a d

O v e r f l o w

t o I n t e r r u p t

T i m e r C o u n t e r 0 / 1

T O N

( T M R S 2 , T M R S 1 , T M R S 0 )

Timer Counter 0/1

W D T

H A L T

W D T

T i m e - o u t

R e s e t

R E S

C o l d

R e s e t

W a r m R e s e t

P o w e r - o n D e t e c t i n g

S S T

1 0 - s t a g e

R i p p l e C o u n t e r

O S C I

Reset Configuration