HT95R22 datasheet(24/52 Pages) HOLTEK

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HT95R22

Rev. 1.00

January 6, 2009

Interrupt Priority

Interrupts, occurring in the interval between the rising

edges of two consecutive T2 pulses, will be serviced on

the latter of the two T2 pulses, if the corresponding inter-

rupts are enabled. In case of simultaneous requests, the

following table shows the priority that is applied. These

can be masked by resetting the EMI bit.

Interrupt Source

All Devices Priority

Reset

External Interrupt

Timer 0 Interrupt

Timer 1 Interrupt

Real Time Clock Interrupt

Multi-function Interrupt

In cases where both external and internal interrupts are

enabled and where an external and internal interrupt oc-

curs simultaneously, the external interrupt will always

have priority and will therefore be serviced first. Suitable

masking of the individual interrupts using the INTC reg-

ister can prevent simultaneous occurrences.

External Interrupt

For an external interrupt to occur, the global interrupt en-

able bit, EMI, and external interrupt enable bit, EEI,

must first be set. An actual external interrupt will take

place when the external interrupt request flag, EIF, is

set, a situation that will occur when a high to low transi-

tion appears on the INT line. When the interrupt is en-

abled, the stack is not full and a high to low transition

appears on the external interrupt pin, a subroutine call to

the external interrupt vector at location 04H, will take

place. When the interrupt is serviced, the external inter-

rupt request flag, EIF, will be automatically reset and the

EMI bit will be automatically cleared to disable other in-

terrupts.

Timer/Event Counter Interrupt

For a Timer/Event Counter interrupt to occur, the global

interrupt enable bit, EMI, and the corresponding timer

interrupt enable bit, ET0I or ET1I, must first be set. An

actual Timer/Event Counter interrupt will take place

when the Timer/Event Counter request flag, T0F or T1F,

is set, a situation that will occur when the Timer/Event

Counter overflows. When the interrupt is enabled, the

stack is not full and a Timer/Event Counter overflow oc-

curs, a subroutine call to the timer interrupt vector at lo-

cation 08H or 0CH, will take place. When the interrupt is

serviced, the timer interrupt request flag, T0F or T1F, will

be automatically reset and the EMI bit will be automati-

cally cleared to disable other interrupts.

Real Time Clock Interrupt

For a Real Time Clock interrupt to occur, the global inter-

rupt enable bit, EMI, and the corresponding real timer

clock interrupt enable bit, RTCI, must first be set. An ac-

tual Real Time Clock interrupt will take place when the

Real Time Clock request flag, RTCF, is set, a situation

that will occur when the RTC times out which will occur

every second. When the interrupt is enabled, the stack

is not full and a Real Time Clock interrupt request oc-

curs, a subroutine call to the real time clock interrupt

vector at location 14H, will take place. When the inter-

rupt is serviced, the timer interrupt request flag, RTCF,

will be automatically reset and the EMI bit will be auto-

matically cleared to disable other interrupts.

Multi-function Interrupt

For a Multi-function interrupt to occur, the global inter-

rupt enable bit, EMI, and the corresponding

multi-function interrupt enable bit, EMFI, must first be

set. An actual Multi-function interrupt will take place

when the Multi-function interrupt request flag, MFF, is

set, a situation that will occur when PC0. When the inter-

rupt is enabled, the stack is not full and a Multi-function

interrupt request occurs, a subroutine call to the

multi-function interrupt vector at location 18H, will take

place. When the interrupt is serviced, the multi-function

interrupt request flag, MFF, will be automatically reset

and the EMI bit will be automatically cleared to disable

other interrupts.

Programming Considerations

By disabling the interrupt enable bits, a requested inter-

rupt can be prevented from being serviced, however,

once an interrupt request flag is set, it will remain in this

condition in the INTC register until the corresponding in-

terrupt is serviced or until the request flag is cleared by a

software instruction.

It is recommended that programs do not use the

²CALL

subroutine

² instruction within the interrupt subroutine.

Interrupts often occur in an unpredictable manner or

need to be serviced immediately in some applications. If

only one stack is left and the interrupt is not well con-

trolled, the original control sequence will be damaged

once a

²CALL subroutine² is executed in the interrupt

subroutine.

All of these interrupts have the capability of waking up

the processor when in the Power Down Mode. Only the

Program Counter is pushed onto the stack. If the con-

tents of the register or status register are altered by the

interrupt service program, which may corrupt the de-

sired control sequence, then the contents should be

saved in advance.

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