HT45F23 datasheet(64/152 Pages) HOLTEK

64 / 152 page

internal clock cycle occurs, the Timer/Event Counter increments by one. When it is full and overflows,

an interrupt signal is generated and the Timer/Event Counter will reload the value already loaded into

the preload register and continue counting. The interrupt can be disabled by ensuring that the

Timer/Event Counter Interrupt Enable bit in the Interrupt Control Register, INTC0, is reset to zero.

Configuring the Event Counter Mode

In this mode, a number of internally changing logic events, occurring on the internal comparators

output, can be recorded by the Timer/Event Counter. To operate in this mode, the Operating Mode

Select bit pair, T0M1/T0M0 or T1M1/T1M0, in the Timer Control Register must be set to the correct

value as shown.

Control Register Operating Mode

Select Bits for the Event Counter Mode

Bit7

Bit6

0/1

In this mode, the comparator output, CMP1OP or CMP2OP, is used as the Timer/Event Counter clock

source, however it is not divided by the internal prescaler. After the other bits in the Timer Control

can be set high to enable the Timer/Event Counter to run. If the Active Edge Select bit T0E or T1E,

which is bit 3 of the Timer Control Register, is low, the Timer/Event Counter will increment each time

the external timer pin receives a low to high transition. If the Active Edge Select bit is high, the counter

will increment each time the external timer pin receives a high to low transition. When it is full and

overflows, an interrupt signal is generated and the Timer/Event Counter will reload the value already

loaded into the preload register and continue counting. The interrupt can be disabled by ensuring that

the Timer/Event Counter Interrupt Enable bit in the Interrupt Control Register, INTC0, is reset to zero.

It should be noted that in the internal event counting mode, even if the microcontroller is in the Power

Down Mode, the Timer/Event Counter will continue to record externally changing logic events on the

timer input pin. As a result when the timer overflows it will generate a timer interrupt and

corresponding wake-up source.

Configuring the Pulse Width Measurement Mode

In this mode, the Timer/Event Counter can be utilised to measure the width of external pulses applied

to the external timer pin. To operate in this mode, the Operating Mode Select bit pair, T0M1/T0M0 or

T1M1/T1M0, in the Timer Control Register must be set to the correct value as shown.

Control Register Operating Mode Select

Bits for the Pulse Width Measurement Mode

Bit7

Bit6

In this mode the internal clock, fSYS , is used as the internal clock for 8-bit Timer/Event Counter 0 and

fSUB or fSYS/4 is used as the internal clock for 16-bit Timer/Event Counter 1. However, the clock source,

fSYS, for 8-bit timer is further divided by a prescaler, the value of which is determined by the Prescaler

Rate Select bits T0PSC2~T0PSC0, which are bits 2~0 in the Timer Control Register. After the other

bits in the Timer Control Register have been setup, the enable bit T0ON or T1ON, which is bit 4 of the

Rev. 1.20

September 15, 2011

HT45F23/HT45F43

8-Bit Flash MCU with Op Amps & Comparators

T i m e r + 2

E x t e r n a l E v e n t o r

I n t e r n a l E v e n t

I n c r e m e n t

T i m e r C o u n t e r

T i m e r + 3

T i m e r + 1

Event Counter Mode Timing Chart (TnE=1)

I n c r e m e n t

T i m e r C o n t r o l l e r

P r e s c a l e r O u t p u t

T i m e r + 1

T i m e r + 2

T i m e r + N

T i m e r + N + 1

Timer Mode Timing Chart

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