MCD212 datasheet(13/87 Pages) MOTOROLA

13 / 87 page

MCD212

1–1

MOTOROLA

GENERAL DESCRIPTION

1.1

INTRODUCTION

The Video Decoder and System Controller with JTAG (VDSC/JTAG) is a CMOS device integrating a

680X0 family system controller and video graphics decoder, see Figure 1–1 below.

The MCD212 is a programmable, multi–scan video device that can function as either a master or a

slave. It is functionally equivalent to the MCD211 with the addition of JTAG testing. The MCD212 is

a drop–in replacement for the MCD211 if the JTAG functionality is not required. It can directly drive up

to 5M bytes1 of memory and provides chip–select signals for system ROM and peripherals. The

on–chip DRAM controller can support up to 4M bytes DRAM and controls access to the unspecialized

System or Video DRAM. The CPU can access any memory location, even during active video display

lines, thereby boosting system performance.

The video image is made up of four separate video planes: the cursor, two graphics planes (A and B),

and one background plane. The video decoder receives two independent video channels from the

Video DRAM. Each channel has a real–time file decoder permitting the display of normal, run–length,

and mosaic compressed files. The resulting files can contain DYUV, CLUT, or direct RGB data. After

decoding the resulting planes, A and B can be combined with a cursor and background allowing for

visual effects like dissolves, mosaics, partial updates, etc., under software control. The resulting dis-

play is available in Red, Green, and Blue components, each being eight bits in length. The display

resolution is programmable up to 768 x 560.

68000 BUS

VDSC

DAC

RGB VIDEO

DRAM

Figure 1–1. System Block Diagram

1. In this document a word is defined as 16 bits and a long–word as 32 bits.

Hexadecimal figures are indicated by an h in front.

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