MSC1202Y2RHHT datasheet(80/92 Pages) TI1

80 / 92 page

MSC1200

MSC1201

MSC1202

SBAS317E − APRIL 2004 − REVISED MAY 2006

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Phase Lock Loop High (PLLH)

Reset Value

SFR F5h

CLKSTAT2

CLKSTAT1

CLKSTAT0

PLLLOCK

PLL9

PLL8

xxh

CLKSTAT2−0

Active Clock Status (read-only). Derived from HCR2 setting; refer to Table 3.

bits 7−5

000: Reserved

001: Reserved

010: Reserved

011: External Clock Mode

100: PLL High-Frequency (HF) Mode (must read PLLLOCK to determine active clock status)

101: PLL Low-Frequency (LF) Mode (must read PLLLOCK to determine active clock status)

110: Internal Oscillator High-Frequency (HF) Mode

111: Internal Oscillator Low-Frequency (LF) Mode

PLLLOCK

PLL Lock Status and Status Enable.

bit 4

For Write (PLL Lock Status Enable):

0 = No Effect

1 = Enable PLL Lock Detection (must wait 20ms before PLLLOCK read status is valid).

For Read (PLL Lock Status):

0 = PLL Not Locked (PLL may be inactive; refer to Table 3 for active clock mode)

1 = PLL Locked (PLL is active clock).

PLL9−8

PLL Counter Value Most Significant 2 Bits (refer to PLLL, SFR F4h).

bits 1−0

Analog Clock (ACLK)

Reset Value

SFR F6h

FREQ6

FREQ5

FREQ4

FREQ3

FREQ2

FREQ1

FREQ0

03h

FREQ6−0

Clock Frequency − 1. This value + 1 divides the system clock to create the ADC clock.

bits 6−0

ACLK +

CLK

ACLK

) 1

, where f

CLK +

OSC

SYSCLK divider

MOD +

ACLK

ADC Data Rate

+ f

DATA +

MOD

Decimation Ratio

System Reset (SRST)

Reset Value

SFR F7h

RSTREQ

00h

RSTREQ

Reset Request. Setting this bit to ‘1’ and then clearing to ‘0’ will generate a system reset.

bit 0

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