1680C—08/26/10

9FG830

Eight Output Differential Frequency Generator for PCIe Gen3 and QPI

12

General SMBus serial interface information for the 9FG830

How to Write:

•

Controller (host) sends a start bit.

• Controller (host) sends the write address DC

(H)

• IDT clock will acknowledge

• Controller (host) sends the begining byte location = N

• IDT clock will acknowledge

• Controller (host) sends the data byte count = X

• IDT clock will acknowledge

• Controller (host) starts sending Byte N through

Byte N + X -1

(see Note 2)

• IDT clock will acknowledge each byte one at a time

• Controller (host) sends a Stop bit

How to Read:

• Controller (host) will send start bit.

• Controller (host) sends the write address DC

(H)

• IDT clock will acknowledge

• Controller (host) sends the begining byte

location = N

• IDT clock will acknowledge

• Controller (host) will send a separate start bit.

• Controller (host) sends the read address DD

(H)

• IDT clock will acknowledge

• IDT clock will send the data byte count = X

• IDT clock sends Byte N + X -1

• IDT clock sends Byte 0 through byte X (if X

(H)

• Controller (host) will need to acknowledge each byte

• Controllor (host) will send a not acknowledge bit

• Controller (host) will send a stop bit

IDT (Sla ve /Re ce ive r)

T

W R

ACK

ACK

ACK

ACK

ACK

P

stoP bit

Index Block Write Operation

B eginning Byte = N

W Rite

starT bit

Controlle r (Host)

Byte N + X - 1

Data Byte Count = X

B eginning Byte N

T

starT bit

W R

W Rite

RT

Repeat starT

RD

ReaD

Beginning B yte N

Byte N + X - 1

N

Not acknowledge

P

stoP bit

Index Block Read Operation

B eginning Byte = N

ACK

ACK

Data Byte Count = X

ACK

IDT (Sla ve /Re ce ive r)

Controlle r (Host)

ACK

ACK