9FG830AFILF datasheet(5/19 Pages) IDT

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IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI

1680C—08/26/10

9FG830

Eight Output Differential Frequency Generator for PCIe Gen3 and QPI

Electrical Characteristics - Absolute Maximum Ratings

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

3.3V Core Supply Voltage

VDDA

4.6

1,2

3.3V Logic Supply Voltage

VDD

4.6

1,2

Input Low Voltage

VIL

GND-0.5

Input High Voltage

VIH

Except for SMBus interface

VDD+0.5V

Input High Voltage

VIHSMB

SMBus clock and data pins

5.5V

Storage Temperature

-65

150

°C

Junction Temperature

125

°C

Input ESD protection

ESD prot

Human Body Model

2000

1Guaranteed by design and characterization, not 100% tested in production.

2 Operation under these conditions is neither implied nor guaranteed.

Electrical Characteristics - Input/Supply/Common Parameters

TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

TCOM

Commmercial range

°C

TIND

Industrial range

-40

°C

Input High Voltage

VIH

Single-ended inputs, except SMBus, low

threshold and tri-level inputs

VDD + 0.3

Input Low Voltage

VIL

Single-ended inputs, except SMBus, low

threshold and tri-level inputs

GND - 0.3

0.8

IIN

Single-ended inputs, VIN = GND, VIN = VDD

-5

IINP

Single-ended inputs

VIN = 0 V; Inputs with internal pull-up resistors

VIN = VDD; Inputs with internal pull-down resistors

-200

200

SEL14M_25M# = 0

MHz

SEL14M_25M# = 1

14.31818

MHz

Pin Inductance

Lpin

CIN

Logic Inputs

1.5

CINXTAL

Crystal inputs

COUT

Output pin capacitance

Clk Stabilization

TSTAB

From VDD Power-Up and after input clock

stabilization or de-assertion of PD# to 1st clock

2.5

1,2

SS Modulation Frequency

fMODIN

Allowable Frequency

(Triangular Modulation)

kHz

OE# Latency

tLATOE#

DIF start after OE# assertion

DIF stop after OE# deassertion

cycles

1,3

Tdrive_STOP#

tDRVDS

DIF output enable after

DIF_STOP# de-assertion

300

1,3

Tfall

Fall time of control inputs

1,2

Trise

Rise time of control inputs

1,2

SMBus Input Low Voltage

VILSMB

0.8

SMBus Input High Voltage

VIHSMB

2.1

VDDSMB

SMBus Output Low Voltage

VOLSMB

@ IPULLUP

0.4

SMBus Sink Current

IPULLUP

@ VOL

Nominal Bus Voltage

VDDSMB

3V to 5V +/- 10%

2.7

5.5

SCLK/SDATA Rise Time

tRSMB

(Max VIL - 0.15) to (Min VIH + 0.15)

1000

SCLK/SDATA Fall Time

tFSMB

(Min VIH + 0.15) to (Max VIL - 0.15)

300

SMBus Operating

Frequency

fMAXSMB

Maximum SMBus operating frequency

100

kHz

1Guaranteed by design and characterization, not 100% tested in production.

2Control input must be monotonic from 20% to 80% of input swing.

Ambient Operating

Temperature

Input Current

3Time from deassertion until outputs are >200 mV

Capacitance

Input Frequency

Fin

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