9FG830AFILF datasheet(6/19 Pages) IDT

6 / 19 page

IDT® Eight Output Differential Frequency Generator for PCIe Gen3 and QPI

1680C—08/26/10

9FG830

Eight Output Differential Frequency Generator for PCIe Gen3 and QPI

Electrical Characteristics - DIF 0.7V Current Mode Differential Outputs

TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%, See Test Loads for loading conditions

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS NOTES

Slew rate

Trf

Scope averaging on

V/ns

1, 2, 3

Slew rate matching

∆Trf

Slew rate matching, Scope averaging on

1, 2, 4

Voltage High

VHigh

660

850

Voltage Low

VLow

-150

150

Max Voltage

Vmax

1150

Min Voltage

Vmin

-300

Vswing

Scope averaging off

300

1, 2

Crossing Voltage (abs)

Vcross_abs

Scope averaging off

250

550

1, 5

Crossing Voltage (var)

∆-Vcross

Scope averaging off

140

1, 6

2 Measured from differential waveform

6 The total variation of all Vcross measurements in a particular system. This is a subset of V_cross_min/max (V_cross absolute)

allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute.

Statistical measurement on single-ended signal

using oscilloscope math function. (Scope

averaging on)

Measurement on single ended signal using

absolute value. (Scope averaging off)

1Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xR

R). For RR = 475

(1%), IREF = 2.32mA.

IOH = 6 x IREF and VOH = 0.7V @ ZO=50 (100 differential impedance).

3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around

differential 0V.

4 Matching applies to rising edge rate of Clock / falling edge rate of Clock#. It is measured in a +/-75mV window centered on the

average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the

oscilloscope uses for the edge rate calculations.

5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising

edge (i.e. Clock rising and Clock# falling).

Electrical Characteristics - Current Consumption

TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%, See Test Loads for loading conditions

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

IDD3.3

VDD, All outputs active @100MHz

250

IDDA3.3OP

VDDA, All outputs active @100MHz

IDD3.3

VDD, All outputs active @400MHz

200

IDDA3.3OP

VDDA, All outputs active @400MHz

IDD3.3DS

VDD, All DIF pairs stopped driven

190

IDDA3.3DS

VDDA, All DIF pairs stopped driven

IDD3.3DZ

VDD, All DIF pairs stopped Hi-Z

IDDA3.3DZ

VDDA, All DIF pairs stopped Hi-Z

1Guaranteed by design and characterization, not 100% tested in production.

2 I

REF = VDD/(3xRR). For RR = 475

(1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50 .

Operating Supply Current

DIF_STOP# Current

Electrical Characteristics - Output Duty Cycle, Jitter, and Skew Characterisitics

TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%, See Test Loads for Loading Conditions

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

Duty Cycle

tDC

Measured differentially, PLL Mode

Skew, Output to Output

tsk3

VT = 50%

Jitter, Cycle to cycle

tjcyc-cyc

25M input

1,3

Jitter, Cycle to cycle

tjcyc-cyc

14.318M input

1,3

1Guaranteed by design and characterization, not 100% tested in production.

2 I

REF = VDD/(3xRR). For RR = 475

(1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50 .

3 Measured from differential waveform

9FG830AFILF датащи(PDF) 6 Page - Integrated Device Technology

9FG830AFILF датащи(HTML) 6 Page - Integrated Device Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

датащи скачать

ссылки URL