HT48R005 datasheet(36/62 Pages) HOLTEK

36 / 62 page

HT48R005/HT46R005

Rev. 1.00

November 29, 2011

When the Timer/Event Counter is read, or if data is writ-

ten to the preload register, the clock is inhibited to avoid

errors, however as this may result in a counting error,

this should be taken into account by the programmer.

Care must be taken to ensure that the timers are prop-

erly initialised before using them for the first time. The

associated timer enable bits in the interrupt control reg-

ister must be properly set otherwise the internal interrupt

associated with the timer will remain inactive. The edge

select, timer mode and clock source control bits in timer

control register must also be correctly set to ensure the

timer is properly configured for the required application.

It is also important to ensure that an initial value is first

loaded into the timer registers before the timer is

switched on; this is because after power-on the initial

values of the timer registers are unknown. After the

timer has been initialized the timer can be turned on and

off by controlling the enable bit in the timer control regis-

ter.

When the Timer/Event Counter overflows, its corre-

sponding interrupt request flag in the interrupt control

is enabled this will in turn generate an interrupt signal.

However irrespective of whether the interrupts are en-

abled or not, a Timer/Event Counter overflow will also

generate a wake-up signal if the device is in a

Power-down condition. This situation may occur if the

Timer/Event Counter is in the Event Counting Mode and

if the external signal continues to change state. In such

a case, the Timer/Event Counter will continue to count

these external events and if an overflow occurs the de-

vice will be woken up from its Power-down condition. To

prevent such a wake-up from occurring, the timer inter-

rupt request flag should first be set high before issuing

the

²HALT² instruction to enter the Power Down Mode.

Timer Program Example

The program shows how the Timer/Event Counter regis-

ters are setup along with how the interrupts are enabled

and managed. Note how the Timer/Event Counter is

turned on, by setting bit 4 of the Timer Control Register.

The Timer/Event Counter can be turned off in a similar

way by clearing the same bit. This example program

sets the Timer/Event Counters to be in the timer mode,

which uses the internal system clock as their clock

source.

· PFD Programming Example

org

04h

; external interrupt vector

org

08h

; Timer Counter interrupt vector

Jmp

tmr0int

; jump here when Timer overflows

org

20h

; main program

;internal Timer interrupt routine

tmr0int:

; Timer main program placed here

begin:

;setup Timer registers

mov

a,09bh

; setup Timer preload value

mov

tmr0,a

mov

a,081h

; setup Timer control register

mov

tmr0c,a

; timer mode and prescaler set to /2

;setup interrupt register

mov

a,005h

; enable master interrupt and timer interrupt

mov

intc0,a

set

tmr0c.4

; start Timer

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