HT48R005 datasheet(19/62 Pages) HOLTEK

19 / 62 page

HT48R005/HT46R005

Rev. 1.00

November 29, 2011

low. During program initialisation, it is important to first

setup the control registers to specify which pins are out-

puts and which are inputs before reading data from or

writing data to the I/O ports. One flexible feature of these

registers is the ability to directly program single bits us-

ing the

²SET [m].i² and ²CLR [m].i² instructions. The

ability to change I/O pins from output to input and vice

versa by manipulating specific bits of the I/O control reg-

isters during normal program operation is a useful fea-

ture of these devices.

System Control Registers

- CTRL0, CTRL1

These registers are used to provide control over various

internal functions. Some of these include the Buzzer

control, external Interrupt edge trigger type and Watch-

dog Timer enable function.

Wake-up Function Register

- PAWK

When the microcontroller enters the Sleep Mode, vari-

ous methods exist to wake the device up and continue

with normal operation. One method is to allow a falling

edge on the I/O pins to have a wake-up function. This

to have this wake-up function.

Pull-high Registers

- PAPU

The I/O pins, if configured as inputs, can have internal

pull-high resistors connected, which eliminates the need

for external pull-high resistors. This register selects which

I/O pins are connected to internal pull-high resistors.

· CTRL0 Register

Bit

76543210

Name

¾¾¾¾

BZEN1

BZEN0

¾¾

R/W

¾¾¾¾

R/W

¾¾

POR

¾¾¾¾

¾¾

Bit 7~4

unimplemented, read as

²0²

Bit 3~2

BZEN1, BZEN0: BZ/BZ enable/disable

00: both disabled

01: Reserved

10: BZ only enabled

11: BZ and BZ enabled

When BZ or BZ is disabled, the I/O port will have general I/O functions. If enabled, the BZ or

BZ outputs will still be controlled by the related I/O port control and data settings. Refer to the

Buzzer Function section for details.

Bit 1~04

unimplemented, read as

²0²

· CTRL1 Register

Bit

76543210

Name

INTEG1

INTEG0

¾¾

WDTEN3

WDTEN2

WDTEN1

WDTEN0

R/W

¾¾

R/W

POR

¾¾

1010

Bit 7, 6

INTEG1, INTEG0: External interrupt edge type

00: disable

01: rising edge trigger

10: falling edge trigger

11: dual edge trigger

Bit 5, 4

unimplemented, read as

²0²

Bit 3~0

WDTEN3, WDTEN2, WDTEN1, WDTEN0: WDT function enable

1010: WDT disabled

Other values: WDT enabled - Recommended value is 0101

If the

²watchdog timer enable² configuration option is selected, then the watchdog timer will

always be enabled and the WDTEN3~WDTEN0 control bits will have no effect.

Note:

The WDT is only disabled when both the WDT configuration option is disabled and when bits

WDTEN3~WDTEN0=1010.

The WDT is enabled when either the WDT configuration option is enabled or when bits

WDTEN3~WDTEN0

¹1010.

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