AT89LP51 datasheet(49/113 Pages) ATMEL

49 / 113 page

3709C–MICRO–5/11

AT89LP51/52 - Preliminary

11.5

Clock Output (Pin Toggle Mode)

On the AT89LP51/52, Timer 0 and Timer 1 may be independently configured to toggle their

respective counter pins, T0 and T1, on overflow by setting the T0OE or T1OE bits in TCONB.

The C/Tx bits must be set to “0” when in toggle mode and the T0 (P3.4) and T1 (P3.5) pins must

be configured in an output mode. The Timer Overflow Flags and Interrupts will continue to func-

tion while in toggle mode and Timer 1 may still generate the baud rate for the UART. The timer

GATE function also works in toggle mode, allowing the output to be halted by an external input.

Toggle mode can be used with Timer Mode 2 to output a 50% duty cycle clock with 8-bit pro-

grammable frequency. Tx is toggled at every Timer x overflow with the pulse width determined

by the value of THx. An example waveform is given in Figure 11-5. The following formula gives

the output frequency for Timer 0 in Mode 2.

Table 11-2.

TCON

– Timer/Counter Control Register

TCON = 88H

Reset Value = 0000 0000B

Bit Addressable

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

Bit

543

Symbol

Function

TF1

Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the processor vectors

to interrupt routine.

TR1

Timer 1 run control bit. Set/cleared by software to turn Timer/Counter on/off.

TF0

Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the processor vectors

to interrupt routine.

TR0

Timer 0 run control bit. Set/cleared by software to turn Timer/Counter on/off.

IE1

Interrupt 1 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed.

IT1

Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts.

IE0

Interrupt 0 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed.

IT0

Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts.

Table 11-3.

TCONB

– Timer/Counter Control Register B

TCONB = 91H

Reset Value = 0000 0000B

Not Bit Addressable

T1OE

T0OE

SPEN

––

–

Bit

543

Symbol

Function

T1OE

Timer 1 Output Enable. Configures Timer 1 to toggle T1 (P3.5) upon overflow.

T0OE

Timer 0 Output Enable. Configures Timer 0 to toggle T0 (P3.4) upon overflow.

SPEN

Enables SPI mode for UART mode 0

Mode 2:

out

System Frequency

2256

TH0

–

()

--------------------------------------------------

TPS

---------------------

AT89LP51 датащи(PDF) 49 Page - ATMEL Corporation

AT89LP51 датащи(HTML) 49 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL