AT89LP51 datasheet(25/113 Pages) ATMEL

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3709C–MICRO–5/11

AT89LP51/52 - Preliminary

Enhanced CPU

The AT89LP51/52 uses an enhanced 8051 CPU that runs at 6 to 12 times the speed of standard

8051 devices (or 3 to 6 times the speed of X2 8051 devices). The increase in performance is

due to two factors. First, the CPU fetches one instruction byte from the code memory every clock

cycle. Second, the CPU uses a simple two-stage pipeline to fetch and execute instructions in

parallel. This basic pipelining concept allows the CPU to obtain up to 1 MIPS per MHz. The

AT89LP51/52 also has a Compatibility mode that preserves the 12-clock machine cycle of stan-

dard 8051s like the AT89S51/52.

5.1

Fast Mode

Fast (Single-Cycle) mode must be enabled by clearing the Compatibility User Fuse. (See “User

Configuration Fuses” on page 86.) In this mode one instruction byte is fetched every system

clock cycle. The 8051 instruction set allows for instructions of variable length from 1 to 3 bytes.

In a single-clock-per-byte-fetch system this means each instruction takes at least as many

clocks as it has bytes to execute. The majority of instructions in the AT89LP51/52 follow this

rule: the instruction execution time in system clock cycles equals the number of bytes per

instruction, with a few exceptions. Branches and Calls require an additional cycle to compute the

target address and some other complex instructions require multiple cycles. See “Instruction Set

Summary” on page 75. for more detailed information on individual instructions.

Example of Fast mode instructions are shown in Figure 5-1. Note that Fast mode instructions

take three times as long to execute if they are fetched from external program memory.

Figure 5-1.

Instruction Execution Sequences in Fast Mode

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